Analysis of network-on-chip topologies for cost-efficient chip multiprocessors
Resumen: As chip multiprocessors accommodate a growing number of cores, they demand interconnection networks that simultaneously provide low latency, high bandwidth, and low power. Our goal is to provide a comprehensive study of the interactions between the interconnection network and the memory hierarchy to enable a better co-design of both components. We explore the implications of the interconnect choice on overall performance by comparing the behaviour of three topologies (mesh, torus, and ring) and their concentrated versions. Simply choosing the concentrated mesh over the ring improves performance by over 40% in a 64-core chip. The key strength of this work is the holistic analysis of the network-on-chip and the memory hierarchy. Experiments are carried out with a full-system simulator that carefully models the processors (single and multithreaded), memory hierarchy, and interconnection network, and executes realistic parallel and multiprogrammed workloads. We corroborate conclusions from several previous works: network diameter is critical, the concentrated mesh offers the best area-energy-delay trade-off, and traffic is very light and highly unbalanced. We also provide interesting insights about application-specific features that are hidden when studying only average results. We include a fairness analysis for multiprogrammed applications, and refute the idea of the memory controller placement greatly affecting performance.
Idioma: Inglés
DOI: 10.1016/j.micpro.2016.01.005
Año: 2016
Publicado en: MICROPROCESSORS AND MICROSYSTEMS 42 (2016), 24-36
ISSN: 0141-9331

Factor impacto JCR: 1.025 (2016)
Categ. JCR: COMPUTER SCIENCE, THEORY & METHODS rank: 68 / 104 = 0.654 (2016) - Q3 - T2
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 196 / 260 = 0.754 (2016) - Q4 - T3
Categ. JCR: COMPUTER SCIENCE, HARDWARE & ARCHITECTURE rank: 40 / 52 = 0.769 (2016) - Q4 - T3

Factor impacto SCIMAGO: 0.225 - Artificial Intelligence (Q3) - Computer Networks and Communications (Q3) - Hardware and Architecture (Q3) - Software (Q4)

Financiación: info:eu-repo/grantAgreement/ES/DGA/T48
Financiación: info:eu-repo/grantAgreement/ES/MEC/FPU12-02553
Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P
Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC
Tipo y forma: Artículo (PostPrint)
Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)

Creative Commons Debe reconocer adecuadamente la autoría, proporcionar un enlace a la licencia e indicar si se han realizado cambios. Puede hacerlo de cualquier manera razonable, pero no de una manera que sugiera que tiene el apoyo del licenciador o lo recibe por el uso que hace. No puede utilizar el material para una finalidad comercial. Si remezcla, transforma o crea a partir del material, no puede difundir el material modificado.


Exportado de SIDERAL (2023-03-23-12:56:21)


Visitas y descargas

Este artículo se encuentra en las siguientes colecciones:
Artículos



 Registro creado el 2017-09-11, última modificación el 2023-03-23


Postprint:
 PDF
Valore este documento:

Rate this document:
1
2
3
 
(Sin ninguna reseña)