000062045 001__ 62045
000062045 005__ 20230323131622.0
000062045 0247_ $$2doi$$a10.1016/j.micpro.2016.01.005
000062045 0248_ $$2sideral$$a94714
000062045 037__ $$aART-2016-94714
000062045 041__ $$aeng
000062045 100__ $$0(orcid)0000-0003-3161-3793$$aOrtín-Obón, Marta$$uUniversidad de Zaragoza
000062045 245__ $$aAnalysis of network-on-chip topologies for cost-efficient chip multiprocessors
000062045 260__ $$c2016
000062045 5060_ $$aAccess copy available to the general public$$fUnrestricted
000062045 5203_ $$aAs chip multiprocessors accommodate a growing number of cores, they demand interconnection networks that simultaneously provide low latency, high bandwidth, and low power. Our goal is to provide a comprehensive study of the interactions between the interconnection network and the memory hierarchy to enable a better co-design of both components. We explore the implications of the interconnect choice on overall performance by comparing the behaviour of three topologies (mesh, torus, and ring) and their concentrated versions. Simply choosing the concentrated mesh over the ring improves performance by over 40% in a 64-core chip. The key strength of this work is the holistic analysis of the network-on-chip and the memory hierarchy. Experiments are carried out with a full-system simulator that carefully models the processors (single and multithreaded), memory hierarchy, and interconnection network, and executes realistic parallel and multiprogrammed workloads. We corroborate conclusions from several previous works: network diameter is critical, the concentrated mesh offers the best area-energy-delay trade-off, and traffic is very light and highly unbalanced. We also provide interesting insights about application-specific features that are hidden when studying only average results. We include a fairness analysis for multiprogrammed applications, and refute the idea of the memory controller placement greatly affecting performance.
000062045 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T48$$9info:eu-repo/grantAgreement/ES/MEC/FPU12-02553$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC
000062045 540__ $$9info:eu-repo/semantics/openAccess$$aby-nc-nd$$uhttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
000062045 590__ $$a1.025$$b2016
000062045 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b68 / 104 = 0.654$$c2016$$dQ3$$eT2
000062045 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b196 / 260 = 0.754$$c2016$$dQ4$$eT3
000062045 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b40 / 52 = 0.769$$c2016$$dQ4$$eT3
000062045 592__ $$a0.225$$b2016
000062045 593__ $$aArtificial Intelligence$$c2016$$dQ3
000062045 593__ $$aComputer Networks and Communications$$c2016$$dQ3
000062045 593__ $$aHardware and Architecture$$c2016$$dQ3
000062045 593__ $$aSoftware$$c2016$$dQ4
000062045 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion
000062045 700__ $$0(orcid)0000-0002-7490-4067$$aSuárez-Gracia, Darío$$uUniversidad de Zaragoza
000062045 700__ $$0(orcid)0000-0003-3000-0506$$aVillarroya-Gaudó, María.$$uUniversidad de Zaragoza
000062045 700__ $$aIzu, Cruz.
000062045 700__ $$0(orcid)0000-0002-5976-1352$$aViñals-Yúfera, Víctor$$uUniversidad de Zaragoza
000062045 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000062045 773__ $$g42 (2016), 24-36$$pMicroprocess. microsyst.$$tMICROPROCESSORS AND MICROSYSTEMS$$x0141-9331
000062045 8564_ $$s419674$$uhttps://zaguan.unizar.es/record/62045/files/texto_completo.pdf$$yPostprint
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000062045 951__ $$a2023-03-23-12:56:21
000062045 980__ $$aARTICLE