000069448 001__ 69448
000069448 005__ 20190529115216.0
000069448 0247_ $$2doi$$a10.1109/TVLSI.2015.2417595
000069448 0248_ $$2sideral$$a91762
000069448 037__ $$aART-2015-91762
000069448 041__ $$aeng
000069448 100__ $$aClemente, Juan Antonio
000069448 245__ $$aHardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems
000069448 260__ $$c2015
000069448 5060_ $$aAccess copy available to the general public$$fUnrestricted
000069448 5203_ $$aThe efficiency of the reconfiguration process in modern field-programmable gate arrays (FPGAs) can improve drastically if an on-chip configuration memory is included in the system, because it can reduce both the reconfiguration latency and its energy consumption. However, the FPGA on-chip memory resources are very limited. Thus, it is very important to manage them effectively in order to improve the reconfiguration process as much as possible, even when the size of the on-chip configuration memory is small. This paper presents a hardware implementation of an on-chip configuration memory controller that efficiently manages run-time reconfigurations. In order to optimize the use of the on-chip memory, this controller includes support to deal with configurations that have been divided into blocks of customizable size. When a reconfiguration must be carried out, our controller provides the blocks stored on-chip and looks for the remaining blocks by accessing to the off-chip configuration memory. Moreover, it dynamically decides which blocks must be stored on-chip. To this end, the designed controller implements a simple but efficient technique that allows maximizing the benefits of the on-chip memories. Experimental results will demonstrate that its implementation cost is very affordable and that it introduces negligible run-time management overheads.
000069448 536__ $$9info:eu-repo/grantAgreement/ES/MINECO/TIN2013-40968-P$$9info:eu-repo/grantAgreement/ES/MINECO/AYA2009-13300$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P$$9info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HiPEAC$$9info:eu-repo/grantAgreement/ES/DGA/T48
000069448 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000069448 590__ $$a1.245$$b2015
000069448 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b19 / 51 = 0.373$$c2015$$dQ2$$eT2
000069448 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b132 / 257 = 0.514$$c2015$$dQ3$$eT2
000069448 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/submittedVersion
000069448 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, Rubén$$uUniversidad de Zaragoza
000069448 700__ $$aChocano, Abel
000069448 700__ $$adel Prado, Carlos
000069448 700__ $$0(orcid)0000-0002-7532-2720$$aResano, Javier$$uUniversidad de Zaragoza
000069448 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000069448 773__ $$g24, 2 (2015), 530 - 543$$pIEEE trans. very large scale integr. (VLSI) syst.$$tIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS$$x1063-8210
000069448 8564_ $$s494316$$uhttp://zaguan.unizar.es/record/69448/files/texto_completo.pdf$$yPreprint
000069448 8564_ $$s131048$$uhttp://zaguan.unizar.es/record/69448/files/texto_completo.jpg?subformat=icon$$xicon$$yPreprint
000069448 909CO $$ooai:zaguan.unizar.es:69448$$particulos$$pdriver
000069448 951__ $$a2019-05-29-11:40:43
000069448 980__ $$aARTICLE