000069465 001__ 69465
000069465 005__ 20210226081039.0
000069465 0247_ $$2doi$$a10.1049/iet-cdt.2016.0095
000069465 0248_ $$2sideral$$a104913
000069465 037__ $$aART-2018-104913
000069465 041__ $$aeng
000069465 100__ $$0(orcid)0000-0002-7752-8714$$aOlivito, Javier$$uUniversidad de Zaragoza
000069465 245__ $$aAnalysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA
000069465 260__ $$c2018
000069465 5060_ $$aAccess copy available to the general public$$fUnrestricted
000069465 5203_ $$aIn this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.
000069465 536__ $$9info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC
000069465 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000069465 590__ $$a0.857$$b2018
000069465 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b75 / 104 = 0.721$$c2018$$dQ3$$eT3
000069465 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b46 / 52 = 0.885$$c2018$$dQ4$$eT3
000069465 592__ $$a0.19$$b2018
000069465 593__ $$aElectrical and Electronic Engineering$$c2018$$dQ3
000069465 593__ $$aSoftware$$c2018$$dQ3
000069465 593__ $$aHardware and Architecture$$c2018$$dQ3
000069465 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/submittedVersion
000069465 700__ $$aSerrano, Felipe
000069465 700__ $$aClemente, Juan Antonio
000069465 700__ $$aMecha, Hortensia
000069465 700__ $$0(orcid)0000-0002-7532-2720$$aResano, Javier$$uUniversidad de Zaragoza
000069465 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000069465 773__ $$g12, 4 (2018), [33 pp]$$pIET Computers and Digital Techniques$$tIET Computers and Digital Techniques$$x1751-8601
000069465 8564_ $$s1018421$$uhttps://zaguan.unizar.es/record/69465/files/texto_completo.pdf$$yPreprint
000069465 8564_ $$s98992$$uhttps://zaguan.unizar.es/record/69465/files/texto_completo.jpg?subformat=icon$$xicon$$yPreprint
000069465 909CO $$ooai:zaguan.unizar.es:69465$$particulos$$pdriver
000069465 951__ $$a2021-02-26-07:56:11
000069465 980__ $$aARTICLE