GPU NTC Process Variation Compensation with Voltage Stacking

Trapani Possignolo, Rafael ; Ebrahimi, Elnaz ; Ardestani, Ehsan ; Sankaranarayanan, Alamelu ; Briz Velasco, Jose Luis (Universidad de Zaragoza) ; Renau, Jose

Resumen: Near-threshold computing (NTC) has the potential to significantly improve efficiency in high throughput architectures, such as general-purpose computing on graphic processing unit (GPGPU). Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without PV management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-PV case, delivering on average (across chips) ˜80 % of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ˜50 % of the nominal performance. We also show that our approach can be applied on top of multifrequency domain designs, improving the overall performance.

Idioma: Inglés

DOI: 10.1109/TVLSI.2018.2831665

Año: 2018

Publicado en: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 26, 9 (2018), 1713-1726
ISSN: 1063-8210

Factor impacto JCR: 1.946 (2018)

Categ. JCR: COMPUTER SCIENCE, HARDWARE & ARCHITECTURE rank: 26 / 52 = 0.5 (2018) - Q2 - T2
Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 146 / 265 = 0.551 (2018) - Q3 - T2

Factor impacto SCIMAGO: 0.405 - Electrical and Electronic Engineering (Q2) - Software (Q2) - Hardware and Architecture (Q2)

Financiación: info:eu-repo/grantAgreement/ES/DGA/T48
Financiación: info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC
Financiación: info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R

Tipo y forma: Article (PostPrint)

Área (Departamento): Área Arquit.Tecnología Comput. (Dpto. Informát.Ingenie.Sistms.)