000084684 001__ 84684 000084684 005__ 20210303162448.0 000084684 0247_ $$2doi$$a10.1016/j.jpdc.2018.10.010 000084684 0248_ $$2sideral$$a109702 000084684 037__ $$aART-2019-109702 000084684 041__ $$aeng 000084684 100__ $$0(orcid)0000-0002-0490-8708$$aFerrerón, A. 000084684 245__ $$aA fault-tolerant last level cache for CMPs operating at ultra-low voltage 000084684 260__ $$c2019 000084684 5060_ $$aAccess copy available to the general public$$fUnrestricted 000084684 5203_ $$aVoltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that allows low-voltage operation by deactivating faulty cache entries, at the expense of reducing the effective cache capacity. In the case of the last-level cache, this capacity reduction leads to an increase in off-chip memory accesses, diminishing the overall energy benefit of reducing the voltage supply. In this work, we exploit the reuse locality and the intrinsic redundancy of multi-level inclusive hierarchies to enhance the performance of block disabling with negligible cost. The proposed fault-aware last-level cache management policy maps critical blocks, those not present in private caches and with a higher probability of being reused, to active cache entries. Our evaluation shows that this fault-aware management results in up to 37.3% and 54.2% fewer misses per kilo instruction (MPKI) than block disabling for multiprogrammed and parallel workloads, respectively. This translates to performance enhancements of up to 13% and 34.6% for multiprogrammed and parallel workloads, respectively. 000084684 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58-17R$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2015-65316-P$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R 000084684 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000084684 590__ $$a2.296$$b2019 000084684 592__ $$a0.525$$b2019 000084684 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b35 / 108 = 0.324$$c2019$$dQ2$$eT1 000084684 593__ $$aArtificial Intelligence$$c2019$$dQ2 000084684 593__ $$aComputer Networks and Communications$$c2019$$dQ2 000084684 593__ $$aHardware and Architecture$$c2019$$dQ2 000084684 593__ $$aSoftware$$c2019$$dQ2 000084684 593__ $$aTheoretical Computer Science$$c2019$$dQ3 000084684 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion 000084684 700__ $$0(orcid)0000-0003-4164-5078$$aAlastruey-Benedé, J.$$uUniversidad de Zaragoza 000084684 700__ $$0(orcid)0000-0002-7490-4067$$aSuárez Gracia, D.$$uUniversidad de Zaragoza 000084684 700__ $$aMonreal Arnal, T. 000084684 700__ $$0(orcid)0000-0002-5916-7898$$aIbáñez Marín, P.$$uUniversidad de Zaragoza 000084684 700__ $$0(orcid)0000-0002-5976-1352$$aViñals Yúfera, V.$$uUniversidad de Zaragoza 000084684 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000084684 773__ $$g125 (2019), 31-44$$pJ. parallel distrib. comput.$$tJOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING$$x0743-7315 000084684 8564_ $$s1745581$$uhttps://zaguan.unizar.es/record/84684/files/texto_completo.pdf$$yPostprint 000084684 8564_ $$s162562$$uhttps://zaguan.unizar.es/record/84684/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000084684 909CO $$ooai:zaguan.unizar.es:84684$$particulos$$pdriver 000084684 951__ $$a2021-03-03-16:11:01 000084684 980__ $$aARTICLE