000088471 001__ 88471 000088471 005__ 20221004075833.0 000088471 0247_ $$2doi$$a10.1007/s11227-019-02768-y 000088471 0248_ $$2sideral$$a110690 000088471 037__ $$aART-2019-110690 000088471 041__ $$aeng 000088471 100__ $$0(orcid)0000-0003-0668-6229$$aDávila Guzmán, M.A.$$uUniversidad de Zaragoza 000088471 245__ $$aCooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL 000088471 260__ $$c2019 000088471 5060_ $$aAccess copy available to the general public$$fUnrestricted 000088471 5203_ $$aHeterogeneous systems are the core architecture of most of the high-performance computing nodes, due to their excellent performance and energy efficiency. However, a key challenge that remains is programmability, specifically, releasing the programmer from the burden of managing data and devices with different architectures. To this end, we extend EngineCL to support FPGA devices. Based on OpenCL, EngineCL is a high-level framework providing load balancing among devices. Our proposal fully integrates FPGAs into the framework, enabling effective cooperation between CPU, GPU, and FPGA. With command overlapping and judicious data management, our work improves performance by up to 96% compared with single-device execution and delivers energy-delay gains of up to 37%. In addition, adopting FPGAs does not require programmers to make big changes in their applications because the extensions do not modify the user-facing interface of EngineCL. 000088471 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T48$$9info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC$$9This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 687698-HiPEAC$$9info:eu-repo/grantAgreement/ES/MEC/FPU16-03299$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-81840-REDT$$9info:eu-repo/grantAgreement/ES/UZ/JIUZ-2017-TEC-09 000088471 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000088471 590__ $$a2.469$$b2019 000088471 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b24 / 53 = 0.453$$c2019$$dQ2$$eT2 000088471 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b123 / 266 = 0.462$$c2019$$dQ2$$eT2 000088471 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b31 / 108 = 0.287$$c2019$$dQ2$$eT1 000088471 592__ $$a0.432$$b2019 000088471 593__ $$aHardware and Architecture$$c2019$$dQ2 000088471 593__ $$aInformation Systems$$c2019$$dQ2 000088471 593__ $$aSoftware$$c2019$$dQ2 000088471 593__ $$aTheoretical Computer Science$$c2019$$dQ3 000088471 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion 000088471 700__ $$aNozal, R. 000088471 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, R.$$uUniversidad de Zaragoza 000088471 700__ $$0(orcid)0000-0003-3000-0506$$aVillarroya-Gaudó, M.$$uUniversidad de Zaragoza 000088471 700__ $$0(orcid)0000-0002-7490-4067$$aSuárez Gracia, D.$$uUniversidad de Zaragoza 000088471 700__ $$aBosque, J.L. 000088471 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000088471 773__ $$g75, 3 (2019), 1732-1746$$pJ. supercomput.$$tJournal of Supercomputing$$x0920-8542 000088471 8564_ $$s539162$$uhttps://zaguan.unizar.es/record/88471/files/texto_completo.pdf$$yPostprint 000088471 8564_ $$s246554$$uhttps://zaguan.unizar.es/record/88471/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000088471 909CO $$ooai:zaguan.unizar.es:88471$$particulos$$pdriver 000088471 951__ $$a2022-10-03-13:17:32 000088471 980__ $$aARTICLE