106589 20210902121933.0 doi 10.1109/TVLSI.2020.3005451 sideral 120311 ART-2020-120311 eng Alcolea Moreno, A. Universidad de Zaragoza (orcid)0000-0002-7057-4283 Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems 2020 Access copy available to the general public Unrestricted Deep neural networks (DNNs) are increasing their presence in a wide range of applications, and their computationally intensive and memory-demanding nature poses challenges, especially for embedded systems. Pruning techniques turn DNN models into sparse by setting most weights to zero, offering optimization opportunities if specific support is included. We propose a novel pipelined architecture for DNNs that avoids all useless operations during the inference process. It has been implemented in a field-programmable gate array (FPGA), and the performance, energy efficiency, and area have been characterized. Exploiting sparsity yields remarkable speedups but also produces area overheads. We have evaluated this tradeoff in order to identify in which scenarios it is better to use that area to exploit sparsity, or to include more computational resources in a conventional DNN architecture. We have also explored different arithmetic bitwidths. Our sparse architecture is clearly superior on 32-bit arithmetic or highly sparse networks. However, on 8-bit arithmetic or networks with low sparsity it is more profitable to deploy a dense architecture with more arithmetic resources than including support for sparsity. We consider that FPGAs are the natural target for DNN sparse accelerators since they can be loaded at run-time with the best-fitting accelerator. info:eu-repo/grantAgreement/ES/DGA/Research Groups-European Social Found info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/CICYT-PID2019-105660RB-C21 info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2016-76635-C2-1-R info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/TIN2017-87237-9 info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 2.312 2020 ENGINEERING, ELECTRICAL & ELECTRONIC 152 / 273 = 0.557 2020 Q3 T2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 27 / 53 = 0.509 2020 Q3 T2 0.506 2020 Electrical and Electronic Engineering 2020 Q2 Software 2020 Q2 Hardware and Architecture 2020 Q2 info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion Olivito, J. Universidad de Zaragoza (orcid)0000-0002-7752-8714 Resano, J. Universidad de Zaragoza (orcid)0000-0002-7532-2720 Mecha, H. 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 28, 9 (2020), 1993-2003 IEEE trans. very large scale integr. (VLSI) syst. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1063-8210 2233166 http://zaguan.unizar.es/record/106589/files/texto_completo.pdf Postprint 3722241 http://zaguan.unizar.es/record/106589/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:106589 articulos driver 2021-09-02-10:56:45 ARTICLE