000107409 001__ 107409 000107409 005__ 20240301150735.0 000107409 0247_ $$2doi$$a10.3390/electronics10091105 000107409 0248_ $$2sideral$$a124863 000107409 037__ $$aART-2021-124863 000107409 041__ $$aeng 000107409 100__ $$0(orcid)0000-0001-5402-1251$$aMartínez Pérez, Antonio Dionisio$$uUniversidad de Zaragoza 000107409 245__ $$aAnalysis of Non-Idealities on CMOS Passive Mixers 000107409 260__ $$c2021 000107409 5060_ $$aAccess copy available to the general public$$fUnrestricted 000107409 5203_ $$aIn the current state of the art, WiFi-alike standards require achieving a high Image Rejection Ratio (IRR) while having low power consumption. Thus, quadrature structures based on passive ring mixers offer an attractive and widely used solution, as they can achieve a high IRR while being a passive block. However, it is not easy for the designer to know when a simple quadrature scheme is enough and when they should aim for a double quadrature structure approach, as the latter can improve the performance at the cost of requiring more area and complexity. This study focuses on the IRR, which crucially depends on the symmetry between the I and Q branches. Non-idealities (component mismatches, parasitics, etc.) will degrade the ideal balance by affecting the mixer and/or following/previous stages. This paper analyses the effect of imbalances, providing the constraints for obtaining a 40 dB IRR in the case of a conversion from a one-hundred-megahertz signal to the five-gigahertz range (upconversion) and vice versa (downconversion) for simple and double quadrature schemes. All simulations were carried out with complete device models from 65 nm standard CMOS technology and also a post-layout Monte Carlo analysis was included for mismatch analysis. The final section includes guidelines to help designers choose the most adequate scheme for each case. 000107409 536__ $$9info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2017-85867-R 000107409 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/ 000107409 590__ $$a2.69$$b2021 000107409 592__ $$a0.59$$b2021 000107409 594__ $$a3.7$$b2021 000107409 591__ $$aCOMPUTER SCIENCE, INFORMATION SYSTEMS$$b100 / 163 = 0.613$$c2021$$dQ3$$eT2 000107409 593__ $$aComputer Networks and Communications$$c2021$$dQ2 000107409 591__ $$aPHYSICS, APPLIED$$b82 / 161 = 0.509$$c2021$$dQ3$$eT2 000107409 593__ $$aSignal Processing$$c2021$$dQ2 000107409 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b139 / 274 = 0.507$$c2021$$dQ3$$eT2 000107409 593__ $$aHardware and Architecture$$c2021$$dQ2 000107409 593__ $$aControl and Systems Engineering$$c2021$$dQ2 000107409 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion 000107409 700__ $$0(orcid)0000-0003-3629-0540$$aAznar, Francisco$$uUniversidad de Zaragoza 000107409 700__ $$0(orcid)0000-0002-2796-7022$$aRoyo, Guillermo$$uUniversidad de Zaragoza 000107409 700__ $$0(orcid)0000-0003-0182-7723$$aCelma, Santiago$$uUniversidad de Zaragoza 000107409 7102_ $$15008$$2250$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Electrónica 000107409 773__ $$g10, 9 (2021), 1105 [10 pp.]$$pElectronics (Basel)$$tElectronics$$x2079-9292 000107409 8564_ $$s2209366$$uhttps://zaguan.unizar.es/record/107409/files/texto_completo.pdf$$yVersión publicada 000107409 8564_ $$s2796740$$uhttps://zaguan.unizar.es/record/107409/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada 000107409 909CO $$ooai:zaguan.unizar.es:107409$$particulos$$pdriver 000107409 951__ $$a2024-03-01-15:05:53 000107409 980__ $$aARTICLE