000109408 001__ 109408
000109408 005__ 20230519145429.0
000109408 0247_ $$2doi$$a10.1109/TC.2021.3115056
000109408 0248_ $$2sideral$$a125530
000109408 037__ $$aART-2021-125530
000109408 041__ $$aeng
000109408 100__ $$0(orcid)0000-0003-0668-6229$$aDávila-Guzmán, María Angélica$$uUniversidad de Zaragoza
000109408 245__ $$aAnalytical Model for Memory-Centric High Level Synthesis-Generated Applications
000109408 260__ $$c2021
000109408 5060_ $$aAccess copy available to the general public$$fUnrestricted
000109408 5203_ $$aHigh performance computing (HPC) demands huge memory bandwidth and computing resources to achieve maximum performance and energy efficiency. FPGAs can provide both, and with the help of High Level Synthesis, those HPC applications can be easily written in high level languages. However, the optimization process remains time-consuming, especially when based on trial-and-error bitstream generation. Model-based performance prediction is a practical and fast approach for kernel optimization, specially if done with information from pre-synthesis reports. This article presents an analytical model focused on memory intensive applications that captures the memory behavior and accurately predicts the kernel execution time within seconds rather than hours, as bitstream generation requires. The model has been validated with two DRAM technologies: DDR4 and HBM2, with a set of microbenchmarks and high performance computing applications showing an average error of 11% for DDR4 and 10% for HBM2. Compared with previous studies, our predictions at least halve the estimation error.
000109408 536__ $$9info:eu-repo/grantAgreement/ES/AEI/PID2019-105660RB-C21-AEI-10.13039-501100011033$$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21
000109408 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000109408 590__ $$a3.183$$b2021
000109408 592__ $$a1.04$$b2021
000109408 594__ $$a5.9$$b2021
000109408 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b114 / 277 = 0.412$$c2021$$dQ2$$eT2
000109408 593__ $$aComputational Theory and Mathematics$$c2021$$dQ1
000109408 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b21 / 55 = 0.382$$c2021$$dQ2$$eT2
000109408 593__ $$aSoftware$$c2021$$dQ1
000109408 593__ $$aHardware and Architecture$$c2021$$dQ1
000109408 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion
000109408 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, Rubén$$uUniversidad de Zaragoza
000109408 700__ $$0(orcid)0000-0003-3000-0506$$aVillarroya-Gaudó, María$$uUniversidad de Zaragoza
000109408 700__ $$0(orcid)0000-0002-7490-4067$$aSuárez Gracia, Darío$$uUniversidad de Zaragoza
000109408 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000109408 773__ $$g70, 12 (2021), 2056-2069$$pIEEE trans. comput.$$tIEEE TRANSACTIONS ON COMPUTERS$$x0018-9340
000109408 8564_ $$s1284179$$uhttps://zaguan.unizar.es/record/109408/files/texto_completo.pdf$$yPostprint
000109408 8564_ $$s3214270$$uhttps://zaguan.unizar.es/record/109408/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint
000109408 909CO $$ooai:zaguan.unizar.es:109408$$particulos$$pdriver
000109408 951__ $$a2023-05-18-14:16:08
000109408 980__ $$aARTICLE