000109451 001__ 109451
000109451 005__ 20230519145429.0
000109451 0247_ $$2doi$$a10.1016/j.sysarc.2021.102304
000109451 0248_ $$2sideral$$a125529
000109451 037__ $$aART-2021-125529
000109451 041__ $$aeng
000109451 100__ $$0(orcid)0000-0003-1550-735X$$aSegarra, Juan$$uUniversidad de Zaragoza
000109451 245__ $$aA generic framework to integrate data caches in the WCET analysis of real-time systems
000109451 260__ $$c2021
000109451 5060_ $$aAccess copy available to the general public$$fUnrestricted
000109451 5203_ $$aWorst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs by temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (set-associative LRU, locked, ACDC, etc.), most of the times adapting techniques designed to analyze instruction caches. On the other hand, there are methodologies to analyze the data reuse of a program, independently of the data cache. In this paper we propose a generic WCET analysis framework to analyze data caches taking profit of such reuse information. It includes the categorization of data references and their integration in an IPET model. We apply it to a conventional LRU cache, an ACDC, and other baseline systems, and compare them using the TACLeBench benchmark suite. Our results show that persistence-based LRU analyses dismiss essential information on data, and a reuse-based analysis improves the WCET bound around 17% in average. In general, the best WCET estimations are obtained with optimization level 2, where the ACDC cache performs 39% better than a set-associative LRU.
000109451 536__ $$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21
000109451 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000109451 590__ $$a5.836$$b2021
000109451 592__ $$a1.283$$b2021
000109451 594__ $$a7.2$$b2021
000109451 591__ $$aCOMPUTER SCIENCE, SOFTWARE ENGINEERING$$b12 / 110 = 0.109$$c2021$$dQ1$$eT1
000109451 593__ $$aSoftware$$c2021$$dQ1
000109451 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b8 / 55 = 0.145$$c2021$$dQ1$$eT1
000109451 593__ $$aHardware and Architecture$$c2021$$dQ1
000109451 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000109451 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, Rubén$$uUniversidad de Zaragoza
000109451 700__ $$0(orcid)0000-0002-5976-1352$$aViñals, Víctor$$uUniversidad de Zaragoza
000109451 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000109451 773__ $$g120 (2021), 102304 [15 pp.]$$pJ. systems archit.$$tJournal of Systems Architecture$$x1383-7621
000109451 8564_ $$s1081002$$uhttps://zaguan.unizar.es/record/109451/files/texto_completo.pdf$$yVersión publicada
000109451 8564_ $$s2667241$$uhttps://zaguan.unizar.es/record/109451/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000109451 909CO $$ooai:zaguan.unizar.es:109451$$particulos$$pdriver
000109451 951__ $$a2023-05-18-14:16:16
000109451 980__ $$aARTICLE