112181 20240319080957.0 doi 10.1016/j.sysarc.2022.102398 sideral 128413 ART-2022-128413 eng Rodríguez, A. Lightweight asynchronous scheduling in heterogeneous reconfigurable systems 2022 Access copy available to the general public Unrestricted The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target in this work, hardware support for shared memory and low-overhead synchronization between the accelerator and the CPU cores make the case for exploring strategies that exploit a tight collaboration between the CPUs and the accelerator. In this paper we propose a novel lightweight scheduling strategy, FastFit, targeted to FPGA accelerators, and a new scheduler based on it, named MultiFastFit, which asynchronously tackles heterogeneous systems comprised of a variety of CPU cores and FPGA IPs. Our strategy significantly reduces the overhead to automatically compute the near-optimal chunksizes when compared to a previous state-of-the-art auto-tuned approach, which makes our approach more suitable for fine-grained applications. Additionally, our scheduler MultiFastFit has been designed to enable the efficient co-execution of work among compute devices in such a way that all the devices are busy while minimizing the load unbalance. Our approaches have been evaluated using four benchmarks carefully tuned for the low-power UltraScale+ platform. Our experiments demonstrate that the FastFit strategy always finds the near-optimal FPGA chunksize for any device configuration at a reasonable cost, even for fine-grained and irregular applications, and that heterogeneous CPU+FPGA co-executions that exploit all the compute devices are usually faster and more energy efficient than the CPU-only and FPGA-only executions. We have also compared MultiFastFit with other state-of-the-art scheduling strategies, finding that it outperforms other auto-tuned approach up to 2x and it achieves similar results to manually-tuned schedulers without requiring an offline search of the ideal CPU-FPGA partition or FPGA chunk granularity. © 2022 The Authors info:eu-repo/grantAgreement/ES/MICINN/PID2019-105396RB-I00 info:eu-repo/semantics/openAccess by http://creativecommons.org/licenses/by/3.0/es/ 4.5 2022 COMPUTER SCIENCE, SOFTWARE ENGINEERING 22 / 108 = 0.204 2022 Q1 T1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 11 / 54 = 0.204 2022 Q1 T1 1.276 2022 Software 2022 Q1 Hardware and Architecture 2022 Q1 8.5 2022 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Navarro, A. Nikov, K. Nunez-Yanez, J. Gran Tejero, R. Universidad de Zaragoza (orcid)0000-0002-4031-5651 Suárez Gracia, D. Universidad de Zaragoza (orcid)0000-0002-7490-4067 Asenjo, R. 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 124 (2022), 102398 [14 pp] J. systems archit. Journal of Systems Architecture 1383-7621 2349544 http://zaguan.unizar.es/record/112181/files/texto_completo.pdf Versión publicada 2577679 http://zaguan.unizar.es/record/112181/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:112181 articulos driver 2024-03-18-13:43:25 ARTICLE