000117153 001__ 117153 000117153 005__ 20240319080956.0 000117153 0247_ $$2doi$$a10.1109/ACCESS.2022.3158356 000117153 0248_ $$2sideral$$a128657 000117153 037__ $$aART-2022-128657 000117153 041__ $$aeng 000117153 100__ $$0(orcid)0000-0001-5402-1251$$aMartinez-Perez, A. D.$$uUniversidad de Zaragoza 000117153 245__ $$aDesign-window methodology for inductorless noise-cancelling CMOS LNAs 000117153 260__ $$c2022 000117153 5060_ $$aAccess copy available to the general public$$fUnrestricted 000117153 5203_ $$aThis paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noise-cancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz. 000117153 536__ $$9info:eu-repo/grantAgreement/ES/AEI/PID2020-114110RA-I00$$9info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2017-85867-R 000117153 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/ 000117153 590__ $$a3.9$$b2022 000117153 592__ $$a0.926$$b2022 000117153 591__ $$aCOMPUTER SCIENCE, INFORMATION SYSTEMS$$b73 / 158 = 0.462$$c2022$$dQ2$$eT2 000117153 591__ $$aTELECOMMUNICATIONS$$b41 / 88 = 0.466$$c2022$$dQ2$$eT2 000117153 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b100 / 274 = 0.365$$c2022$$dQ2$$eT2 000117153 593__ $$aComputer Science (miscellaneous)$$c2022$$dQ1 000117153 593__ $$aMaterials Science (miscellaneous)$$c2022$$dQ1 000117153 593__ $$aEngineering (miscellaneous)$$c2022$$dQ1 000117153 594__ $$a9.0$$b2022 000117153 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion 000117153 700__ $$0(orcid)0000-0003-3629-0540$$aAznar, F.$$uUniversidad de Zaragoza 000117153 700__ $$aFlandre, D. 000117153 700__ $$0(orcid)0000-0003-0182-7723$$aCelma, S.$$uUniversidad de Zaragoza 000117153 7102_ $$15008$$2250$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Electrónica 000117153 773__ $$g10 (2022), 29482-29492$$pIEEE Access$$tIEEE Access$$x2169-3536 000117153 8564_ $$s1487570$$uhttps://zaguan.unizar.es/record/117153/files/texto_completo.pdf$$yVersión publicada 000117153 8564_ $$s2730368$$uhttps://zaguan.unizar.es/record/117153/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada 000117153 909CO $$ooai:zaguan.unizar.es:117153$$particulos$$pdriver 000117153 951__ $$a2024-03-18-13:37:31 000117153 980__ $$aARTICLE