000118062 001__ 118062
000118062 005__ 20250214141227.0
000118062 0247_ $$2doi$$a10.1016/j.sysarc.2022.102553
000118062 0248_ $$2sideral$$a128827
000118062 037__ $$aART-2022-128827
000118062 041__ $$aeng
000118062 100__ $$0(orcid)0000-0001-8606-7609$$aLanderos Muñoz, N.
000118062 245__ $$aGated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators
000118062 260__ $$c2022
000118062 5060_ $$aAccess copy available to the general public$$fUnrestricted
000118062 5203_ $$aNegative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are two of the main reliability threats in current technology nodes. These aging phenomena degrade the transistor''s threshold voltage (Vth) over the lifetime of a digital circuit, resulting in slower transistors that eventually lead to a faulty operation when the critical paths become longer than the processor cycle time. Among all the transistors on a chip, the most vulnerable transistors to such wearout effects are those used to implement SRAM storage, since memory cells are continuously degrading. In particular, NBTI ages PMOS cell transistors when a given logic value is stored for a long period (i.e., a long duty cycle), whereas HCI ages NMOS cell transistors not only when the stored value flips but also when it is accessed. This work focuses on mitigating aging in the on-chip SRAM memories of Convolutional Neural Network (CNN) accelerators storing activations. This paper makes two main contributions. At the software level, we quantify the aging induced by current CNN benchmarks with a characterization study of duty cycle, flip, and access patterns in every activation memory cell. Based on the insights from this study, this work proposes a novel microarchitectural technique, Gated-CNN, that ensures a uniform aging degradation of every memory cell. To do so, Gated-CNN exploits power-gating and address rotation techniques tailored to the memory demands and temporal/spatial localities exhibited by CNN applications, as well as the memory organization and management of CNN accelerators. Experimental results show that, compared to a conventional design, the average Vth degradation savings are at least as much as 49% depending on the type of transistor.
000118062 536__ $$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21
000118062 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000118062 590__ $$a4.5$$b2022
000118062 592__ $$a1.276$$b2022
000118062 591__ $$aCOMPUTER SCIENCE, SOFTWARE ENGINEERING$$b22 / 108 = 0.204$$c2022$$dQ1$$eT1
000118062 593__ $$aSoftware$$c2022$$dQ1
000118062 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b11 / 54 = 0.204$$c2022$$dQ1$$eT1
000118062 593__ $$aHardware and Architecture$$c2022$$dQ1
000118062 594__ $$a8.5$$b2022
000118062 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000118062 700__ $$0(orcid)0000-0002-0824-5833$$aValero, A.$$uUniversidad de Zaragoza
000118062 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, R.$$uUniversidad de Zaragoza
000118062 700__ $$aZoni, D.
000118062 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000118062 773__ $$g128 (2022), 102553 [13 pp.]$$pJ. systems archit.$$tJournal of Systems Architecture$$x1383-7621
000118062 8564_ $$s1354723$$uhttps://zaguan.unizar.es/record/118062/files/texto_completo.pdf$$yVersión publicada
000118062 8564_ $$s2677147$$uhttps://zaguan.unizar.es/record/118062/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000118062 909CO $$ooai:zaguan.unizar.es:118062$$particulos$$pdriver
000118062 951__ $$a2025-02-14-14:11:19
000118062 980__ $$aARTICLE