118062 20250214141227.0 doi 10.1016/j.sysarc.2022.102553 sideral 128827 ART-2022-128827 eng Landeros Muñoz, N. (orcid)0000-0001-8606-7609 Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 2022 Access copy available to the general public Unrestricted Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are two of the main reliability threats in current technology nodes. These aging phenomena degrade the transistor''s threshold voltage (Vth) over the lifetime of a digital circuit, resulting in slower transistors that eventually lead to a faulty operation when the critical paths become longer than the processor cycle time. Among all the transistors on a chip, the most vulnerable transistors to such wearout effects are those used to implement SRAM storage, since memory cells are continuously degrading. In particular, NBTI ages PMOS cell transistors when a given logic value is stored for a long period (i.e., a long duty cycle), whereas HCI ages NMOS cell transistors not only when the stored value flips but also when it is accessed. This work focuses on mitigating aging in the on-chip SRAM memories of Convolutional Neural Network (CNN) accelerators storing activations. This paper makes two main contributions. At the software level, we quantify the aging induced by current CNN benchmarks with a characterization study of duty cycle, flip, and access patterns in every activation memory cell. Based on the insights from this study, this work proposes a novel microarchitectural technique, Gated-CNN, that ensures a uniform aging degradation of every memory cell. To do so, Gated-CNN exploits power-gating and address rotation techniques tailored to the memory demands and temporal/spatial localities exhibited by CNN applications, as well as the memory organization and management of CNN accelerators. Experimental results show that, compared to a conventional design, the average Vth degradation savings are at least as much as 49% depending on the type of transistor. info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R info:eu-repo/grantAgreement/ES/MINECO-AEI-ERDF/PID2019-105660RB-C21 info:eu-repo/semantics/openAccess by http://creativecommons.org/licenses/by/3.0/es/ 4.5 2022 COMPUTER SCIENCE, SOFTWARE ENGINEERING 22 / 108 = 0.204 2022 Q1 T1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 11 / 54 = 0.204 2022 Q1 T1 1.276 2022 Software 2022 Q1 Hardware and Architecture 2022 Q1 8.5 2022 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Valero, A. Universidad de Zaragoza (orcid)0000-0002-0824-5833 Gran Tejero, R. Universidad de Zaragoza (orcid)0000-0002-4031-5651 Zoni, D. 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 128 (2022), 102553 [13 pp.] J. systems archit. Journal of Systems Architecture 1383-7621 1354723 http://zaguan.unizar.es/record/118062/files/texto_completo.pdf Versión publicada 2677147 http://zaguan.unizar.es/record/118062/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:118062 articulos driver 2025-02-14-14:11:19 ARTICLE