120154 20221213161034.0 doi 10.1109/MICRO56248.2022.00072 sideral 131192 ART-2022-131192 eng Navarro-Torres, Agustin Universidad de Zaragoza Berti: an Accurate Local-Delta Data Prefetcher 2022 Data prefetching is a technique that plays a crucial role in modern high-performance processors by hiding long latency memory accesses. Several state-of-the-art hardware prefetchers exploit the concept of deltas, defined as the difference between the cache line addresses of two demand accesses. Existing delta prefetchers, such as best offset prefetching (BOP) and multi-lookahead prefetching (MLOP), train and predict future accesses based on global deltas. We observed that the use of global deltas results in missed opportunities to anticipate memory accesses. In this paper, we propose Berti, a first-level data cache prefetcher that selects the best local deltas, i.e., those that consider only demand accesses issued by the same instruction. Thanks to a high-confidence mechanism that precisely detects the timely local deltas with high coverage, Berti generates accurate prefetch requests. Then, it orchestrates the prefetch requests to the memory hierarchy, using the selected deltas. Our empirical results using ChampSim and SPEC CPU2017 and GAP workloads show that, with a storage overhead of just 2.55 KB, Berti improves performance by 8.5% compared to a baseline IP-stride and 3.5% compared to IPCP, a state-of-the-art prefetcher. Our evaluation also shows that Berti reduces dynamic energy at the memory hierarchy by 33.6% compared to IPCP, thanks to its high prefetch accuracy. Access copy available to the general public Unrestricted info:eu-repo/grantAgreement/ES/AEI-FEDER/PID2019-105660RB-C21 info:eu-repo/grantAgreement/ES/AEI-FEDER/RTI2018-098156-B-C53 info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R info:eu-repo/grantAgreement/EC/H2020/819134/EU/Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures/ECHO This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 819134-ECHO info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion Panda, Biswabandan Alastruey-Benede, Jesus Universidad de Zaragoza (orcid)0000-0003-4164-5078 Ibañez, Pablo Universidad de Zaragoza (orcid)0000-0002-5916-7898 Viñals-Yufera, Victor Universidad de Zaragoza (orcid)0000-0002-5976-1352 Ros, Alberto 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 55 (2022), 975-991 Proceedings of the Annual International Symposium on Microarchitecture, MICRO 1072-4451 800357 http://zaguan.unizar.es/record/120154/files/texto_completo.pdf Postprint 2731914 http://zaguan.unizar.es/record/120154/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:120154 articulos driver 2022-12-13-14:05:33 ARTICLE