000124424 001__ 124424
000124424 005__ 20241125101134.0
000124424 0247_ $$2doi$$a10.1007/s11227-023-05070-0
000124424 0248_ $$2sideral$$a132860
000124424 037__ $$aART-2023-132860
000124424 041__ $$aeng
000124424 100__ $$aNavarro-Torres, Agustín
000124424 245__ $$aBalancer: bandwidth allocation and cache partitioning for multicore processors
000124424 260__ $$c2023
000124424 5060_ $$aAccess copy available to the general public$$fUnrestricted
000124424 5203_ $$aThe management of shared resources in multicore processors is an open problem due to the continuous evolution of these systems. The trend toward increasing the number of cores and organizing them in clusters sets out new challenges not considered in previous works. In this paper, we characterize the use of the shared cache and memory bandwidth of an AMD Rome processor executing multiprogrammed workloads and propose several mechanisms that control the use of these resources to improve the system performance and fairness. Our control mechanisms require no hardware or operating system modifications. We evaluate Balancer on a real system running SPEC CPU2006 and CPU2017 applications. Balancer tuned for performance shows an average increase of 7.1% in system performance and an unfairness reduction of 18.6% with respect to a system without any control mechanism. Balancer tuned for fairness decreases the performance by 1.3% in exchange for a 64.5% reduction of unfairness.
000124424 536__ $$9info:eu-repo/grantAgreement/ES/AEI/PID2019-105660RB-C21-AEI-10.13039-501100011033$$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R$$9info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón
000124424 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000124424 590__ $$a2.5$$b2023
000124424 592__ $$a0.763$$b2023
000124424 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b28 / 59 = 0.475$$c2023$$dQ2$$eT2
000124424 593__ $$aHardware and Architecture$$c2023$$dQ2
000124424 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b166 / 353 = 0.47$$c2023$$dQ2$$eT2
000124424 593__ $$aTheoretical Computer Science$$c2023$$dQ2
000124424 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b48 / 144 = 0.333$$c2023$$dQ2$$eT2
000124424 593__ $$aSoftware$$c2023$$dQ2
000124424 593__ $$aInformation Systems$$c2023$$dQ2
000124424 594__ $$a6.3$$b2023
000124424 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000124424 700__ $$0(orcid)0000-0003-4164-5078$$aAlastruey-Benedé, Jesús$$uUniversidad de Zaragoza
000124424 700__ $$0(orcid)0000-0002-5916-7898$$aIbáñez, Pablo$$uUniversidad de Zaragoza
000124424 700__ $$0(orcid)0000-0002-5976-1352$$aViñals-Yúfera, Víctor$$uUniversidad de Zaragoza
000124424 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000124424 773__ $$g79 (2023), 10252–10276$$pJ. supercomput.$$tJournal of Supercomputing$$x0920-8542
000124424 8564_ $$s1903782$$uhttps://zaguan.unizar.es/record/124424/files/texto_completo.pdf$$yVersión publicada
000124424 8564_ $$s1043547$$uhttps://zaguan.unizar.es/record/124424/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000124424 909CO $$ooai:zaguan.unizar.es:124424$$particulos$$pdriver
000124424 951__ $$a2024-11-22-12:00:08
000124424 980__ $$aARTICLE