124424 20241125101134.0 doi 10.1007/s11227-023-05070-0 sideral 132860 ART-2023-132860 eng Navarro-Torres, Agustín Balancer: bandwidth allocation and cache partitioning for multicore processors 2023 Access copy available to the general public Unrestricted The management of shared resources in multicore processors is an open problem due to the continuous evolution of these systems. The trend toward increasing the number of cores and organizing them in clusters sets out new challenges not considered in previous works. In this paper, we characterize the use of the shared cache and memory bandwidth of an AMD Rome processor executing multiprogrammed workloads and propose several mechanisms that control the use of these resources to improve the system performance and fairness. Our control mechanisms require no hardware or operating system modifications. We evaluate Balancer on a real system running SPEC CPU2006 and CPU2017 applications. Balancer tuned for performance shows an average increase of 7.1% in system performance and an unfairness reduction of 18.6% with respect to a system without any control mechanism. Balancer tuned for fairness decreases the performance by 1.3% in exchange for a 64.5% reduction of unfairness. info:eu-repo/grantAgreement/ES/AEI/PID2019-105660RB-C21-AEI-10.13039-501100011033 info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R info:eu-repo/grantAgreement/ES/DGA-FEDER/Construyendo Europa desde Aragón info:eu-repo/semantics/openAccess by http://creativecommons.org/licenses/by/3.0/es/ 2.5 2023 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 28 / 59 = 0.475 2023 Q2 T2 ENGINEERING, ELECTRICAL & ELECTRONIC 166 / 353 = 0.47 2023 Q2 T2 COMPUTER SCIENCE, THEORY & METHODS 48 / 144 = 0.333 2023 Q2 T2 0.763 2023 Hardware and Architecture 2023 Q2 Theoretical Computer Science 2023 Q2 Software 2023 Q2 Information Systems 2023 Q2 6.3 2023 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Alastruey-Benedé, Jesús Universidad de Zaragoza (orcid)0000-0003-4164-5078 Ibáñez, Pablo Universidad de Zaragoza (orcid)0000-0002-5916-7898 Viñals-Yúfera, Víctor Universidad de Zaragoza (orcid)0000-0002-5976-1352 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 79 (2023), 10252–10276 J. supercomput. Journal of Supercomputing 0920-8542 1903782 http://zaguan.unizar.es/record/124424/files/texto_completo.pdf Versión publicada 1043547 http://zaguan.unizar.es/record/124424/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:124424 articulos driver 2024-11-22-12:00:08 ARTICLE