000129348 001__ 129348 000129348 005__ 20231215094309.0 000129348 0247_ $$2doi$$a10.1109/DCIS55711.2022.9970050 000129348 0248_ $$2sideral$$a132433 000129348 037__ $$aART-2022-132433 000129348 041__ $$aeng 000129348 100__ $$0(orcid)0000-0002-7490-4067$$aSuárez Gracia, D.$$uUniversidad de Zaragoza 000129348 245__ $$aPeRISCVcope: a tiny teaching-oriented RISC-V interpreter 000129348 260__ $$c2022 000129348 5060_ $$aAccess copy available to the general public$$fUnrestricted 000129348 5203_ $$aThe fast advances of computer systems translate into a growing demand of methodologies and tools to introduce those novelties into classes. Among the plethora of those advances, virtualization has become an essential technology in almost every relevant system stack, from connected cars to hyperscaled cloud servers. However, introducing those technologies into the classroom remains a challenging task because of the huge complexity of their software components that may hinder the learning process of students. peRISCVcope aims to help in this area by proposing a tiny yet powerful interpreter to dig into virtualization technologies, such as the implementation of trap&emulate hypervisors. With less than 2,000 lines of code, and thanks to the conciseness of the RV32I base instruction set of RISC-V, peRISCVcope enables students to make virtualization knowledge their own. This paper presents our experiences developing and testing a virtualization laboratory where students implement parts of an interpreter. After the practical experience, peRISCVcope has been proved as a useful pedagogical tool, and, most importantly, students have positively rated the experience. 000129348 536__ $$9info:eu-repo/grantAgreement/ES/AEI/PID2019-105660RB-C21-AEI-10.13039-501100011033$$9info:eu-repo/grantAgreement/ES/DGA-ESF/T58-20R 000129348 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000129348 655_4 $$ainfo:eu-repo/semantics/conferenceObject$$vinfo:eu-repo/semantics/acceptedVersion 000129348 700__ $$0(orcid)0000-0002-0824-5833$$aValero, A.$$uUniversidad de Zaragoza 000129348 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, R.$$uUniversidad de Zaragoza 000129348 700__ $$0(orcid)0000-0003-3000-0506$$aVillarroya, M.$$uUniversidad de Zaragoza 000129348 700__ $$0(orcid)0000-0002-5976-1352$$aViñals, V.$$uUniversidad de Zaragoza 000129348 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000129348 773__ $$g37th (2022), 22363499[6 pp.]$$pProceedings (Conf. Des. Circuits Integr. Syst.)$$tProceedings (Conference on Design of Circuits and Integrated Systems)$$x2471-6170 000129348 8564_ $$s142700$$uhttps://zaguan.unizar.es/record/129348/files/texto_completo.pdf$$yPostprint 000129348 8564_ $$s3129098$$uhttps://zaguan.unizar.es/record/129348/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000129348 909CO $$ooai:zaguan.unizar.es:129348$$particulos$$pdriver 000129348 951__ $$a2023-12-14-13:19:46 000129348 980__ $$aARTICLE