131704 20260217205444.0 doi 10.1016/j.micpro.2024.105023 sideral 136807 ART-2024-136807 eng Toca-Díaz, Yamilka Universidad de Zaragoza Flip-and-Patch: A Fault-Tolerant Technique for On-Chip Memories of CNN Accelerators at Low Supply Voltage 2024 Access copy available to the general public Unrestricted Aggressively reducing the supply voltage () below the safe threshold voltage () can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes. This work addresses the impact of permanent faults on the accuracy of a Convolutional Neural Network (CNN) inference accelerator using on-chip activation memories supplied at low below Based on a characterization study of fault patterns, this paper proposes two low-cost microarchitectural techniques, namely Flip-and-Patch, which maintain the original accuracy of CNN applications even in the presence of a high number of faults caused by operating at. Unlike existing techniques, Flip-and-Patch remains transparent to the programmer and does not rely on application characteristics, making it easily applicable to real CNN accelerators. Experimental results show that Flip-and-Patch ensures the original CNN accuracy with a minimal impact on system performance (less than 0.05% for every application), while achieving average energy savings of 10.5% and 46.6% in activation memories compared to a conventional accelerator operating at safe and nominal supply voltages, respectively. Compared to the state-of-the-art ThUnderVolt technique, which dynamically adjusts the supply voltage at run time and discarding any energy overhead for such an approach, the average energy savings are by 3.2%. info:eu-repo/grantAgreement/ES/AEI-FEDER/PID2019-105660RB-C21 info:eu-repo/grantAgreement/ES/DGA/T58-23R info:eu-repo/semantics/openAccess by https://creativecommons.org/licenses/by/4.0/deed.es 2.6 2024 COMPUTER SCIENCE, THEORY & METHODS 54 / 147 = 0.367 2024 Q2 T2 ENGINEERING, ELECTRICAL & ELECTRONIC 174 / 368 = 0.473 2024 Q2 T2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 31 / 60 = 0.517 2024 Q3 T2 0.493 2024 Computer Networks and Communications 2024 Q2 Software 2024 Q2 Hardware and Architecture 2024 Q2 Artificial Intelligence 2024 Q3 8.2 2024 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Hernández Palacios, Reynier Gran Tejero, Rubén Universidad de Zaragoza (orcid)0000-0002-4031-5651 Valero, Alejandro Universidad de Zaragoza (orcid)0000-0002-0824-5833 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 106 (2024), 105023 [13 pp.] Microprocess. microsyst. MICROPROCESSORS AND MICROSYSTEMS 0141-9331 1334433 http://zaguan.unizar.es/record/131704/files/texto_completo.pdf Versión publicada 2572433 http://zaguan.unizar.es/record/131704/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:131704 articulos driver 2026-02-17-20:17:30 ARTICLE