000144785 001__ 144785 000144785 005__ 20240906111329.0 000144785 0247_ $$2doi$$a10.1109/ACCESS.2024.3440828 000144785 0248_ $$2sideral$$a139564 000144785 037__ $$aART-2024-139564 000144785 041__ $$aeng 000144785 100__ $$aGalilea Torres-Macías, Alitzel 000144785 245__ $$aFast IEEE802.1Qbv Gate Scheduling Through Integer Linear Programming 000144785 260__ $$c2024 000144785 5060_ $$aAccess copy available to the general public$$fUnrestricted 000144785 5203_ $$aTime-Sensitive Networking (TSN) is an in-development technology that enables predictability over Ethernet or wireless networks. Network interfaces compliant with the IEEE 802.1Qbv standard provide different queues/gates on each bridge egress port. In this way, a global network schedule can be set by defining the opening and closing times (Gate Control List, GCL) for each gate. In this paper, we propose a new method to schedule GCLs by dividing the problem into several subproblems. We use Weighted Fair Queuing (WFQ) to set the ordering of frames, and then generate an Integer Linear Programming (ILP) model to optimize the TSN scenario. Next, we assign gates to the scheduled windows, trying to ensure frame isolation whenever possible. Our results show that we can schedule GCLs around 2 times faster than previous studies and up to 5.5 orders of magnitude faster if we choose to obtain any valid solution instead of the optimal one. In addition, we are able to schedule systems with utilization up to 85%, whereas previous papers reach 65%. Moreover, our approach does not need to predefine the number of windows or gates, as required by other methods. 000144785 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58_23R$$9info:eu-repo/grantAgreement/ES/MICINN/PID2022-136454NB-C22 000144785 540__ $$9info:eu-repo/semantics/openAccess$$aby-nc-nd$$uhttp://creativecommons.org/licenses/by-nc-nd/3.0/es/ 000144785 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion 000144785 700__ $$0(orcid)0000-0003-1550-735X$$aSegarra Flor, Juan$$uUniversidad de Zaragoza 000144785 700__ $$0(orcid)0000-0001-5940-9837$$aBriz Velasco, José Luis$$uUniversidad de Zaragoza 000144785 700__ $$aRamírez-Treviño, Antonio 000144785 700__ $$aBlanco-Alcaine, Héctor 000144785 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000144785 773__ $$g12 (2024), 111239-111250$$pIEEE Access$$tIEEE Access$$x2169-3536 000144785 787__ $$tExperimental artifacts$$whttps://codeocean.com/capsule/9965700/tree/v1 000144785 8564_ $$s1509614$$uhttps://zaguan.unizar.es/record/144785/files/texto_completo.pdf$$yVersión publicada 000144785 8564_ $$s2495657$$uhttps://zaguan.unizar.es/record/144785/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada 000144785 909CO $$ooai:zaguan.unizar.es:144785$$particulos$$pdriver 000144785 951__ $$a2024-09-06-10:26:01 000144785 980__ $$aARTICLE