000147717 001__ 147717
000147717 005__ 20241220131257.0
000147717 0247_ $$2doi$$a10.1016/j.sysarc.2024.103292
000147717 0248_ $$2sideral$$a141118
000147717 037__ $$aART-2024-141118
000147717 041__ $$aeng
000147717 100__ $$aToca-Díaz, Yamilka$$uUniversidad de Zaragoza
000147717 245__ $$aShift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators
000147717 260__ $$c2024
000147717 5060_ $$aAccess copy available to the general public$$fUnrestricted
000147717 5203_ $$aUnderscaling the supply voltage () to ultra-low levels below the safe-operation threshold voltage () holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at , respectively.
000147717 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58_23R$$9info:eu-repo/grantAgreement/ES/MICINN/PID2022-136454NB-C22
000147717 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/
000147717 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000147717 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, Rubén$$uUniversidad de Zaragoza
000147717 700__ $$0(orcid)0000-0002-0824-5833$$aValero, Alejandro$$uUniversidad de Zaragoza
000147717 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000147717 773__ $$g157 (2024), 103292 [10 pp.]$$pJ. systems archit.$$tJournal of Systems Architecture$$x1383-7621
000147717 8564_ $$s1405786$$uhttps://zaguan.unizar.es/record/147717/files/texto_completo.pdf$$yVersión publicada
000147717 8564_ $$s2641468$$uhttps://zaguan.unizar.es/record/147717/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000147717 909CO $$ooai:zaguan.unizar.es:147717$$particulos$$pdriver
000147717 951__ $$a2024-12-20-12:02:26
000147717 980__ $$aARTICLE