147717 20260217205609.0 doi 10.1016/j.sysarc.2024.103292 sideral 141118 ART-2024-141118 eng Toca-Díaz, Yamilka Universidad de Zaragoza Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators 2024 Access copy available to the general public Unrestricted Underscaling the supply voltage () to ultra-low levels below the safe-operation threshold voltage () holds promise for substantial power savings in digital CMOS circuits. However, these benefits come with pronounced challenges due to the heightened risk of bitcell permanent faults stemming from process variations in current technology node sizes. This work delves into the repercussions of such faults on the accuracy of a 16-bit fixed-point Convolutional Neural Network (CNN) inference accelerator powering on-chip activation memories at ultra-low voltages. Through an in-depth examination of fault patterns, memory usage, and statistical analysis of activation values, this paper introduces Shift-and-Safe: two novel and cost-effective microarchitectural techniques exploiting the presence of outlier activation values and the underutilization of activation memories. Particularly, activation outliers enable a shift-based data representation that reduces the impact of faults on the activation values, whereas the memory underutilization is exploited to maintain a safe replica of affected activations in idle memory regions. Remarkably, these mechanisms do not add any burden to the programmer and are independent of application characteristics, rendering them easily deployable across real-world CNN accelerators. Experimental results show that Shift-and-Safe maintains the CNN accuracy even in the presence of almost a quarter of the total activations with faults. In addition, average energy savings are by 5% and 11% compared to the state-of-the-art approach and a conventional accelerator supplied at , respectively. info:eu-repo/grantAgreement/ES/DGA/T58-23R info:eu-repo/grantAgreement/ES/MICINN/PID2022-136454NB-C22 info:eu-repo/semantics/openAccess by https://creativecommons.org/licenses/by/4.0/deed.es 4.1 2024 COMPUTER SCIENCE, SOFTWARE ENGINEERING 23 / 129 = 0.178 2024 Q1 T1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 13 / 60 = 0.217 2024 Q1 T1 1.22 2024 Software 2024 Q1 Hardware and Architecture 2024 Q1 10.5 2024 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Gran Tejero, Rubén Universidad de Zaragoza (orcid)0000-0002-4031-5651 Valero, Alejandro Universidad de Zaragoza (orcid)0000-0002-0824-5833 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 157 (2024), 103292 [10 pp.] J. systems archit. Journal of Systems Architecture 1383-7621 1405786 http://zaguan.unizar.es/record/147717/files/texto_completo.pdf Versión publicada 2641468 http://zaguan.unizar.es/record/147717/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:147717 articulos driver 2026-02-17-20:48:14 ARTICLE