Aznar, F. (Universidad de Zaragoza) ; Celma, S. (Universidad de Zaragoza) ; Calvo, B. (Universidad de Zaragoza)
Resumen: This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mVp–p with a BER of 10−12 at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mVp–p to 800 mVp–p, indicating a BER of 10−12. The chip core area is 0.3 × 0.3 mm2 and it consumes 58 mW with a single supply voltage of 1.8 V Idioma: Inglés DOI: 10.1016/j.microrel.2011.02.001 Año: 2011 Publicado en: MICROELECTRONICS RELIABILITY 51, 5 (2011), 959-964 ISSN: 0026-2714 Factor impacto JCR: 1.167 (2011) Categ. JCR: ENGINEERING, ELECTRICAL & ELECTRONIC rank: 112 / 245 = 0.457 (2011) - Q2 - T2 Categ. JCR: NANOSCIENCE & NANOTECHNOLOGY rank: 47 / 66 = 0.712 (2011) - Q3 - T3 Categ. JCR: PHYSICS, APPLIED rank: 71 / 124 = 0.573 (2011) - Q3 - T2 Financiación: info:eu-repo/grantAgreement/ES/MICINN-FEDER/TEC2008-05455/TEC Tipo y forma: Artículo (Versión definitiva) Área (Departamento): Área Electrónica (Dpto. Ingeniería Electrón.Com.)