151511 20251017144640.0 doi 10.1109/TC.2025.3533086 sideral 143118 ART-2025-143118 eng Navarro-Torres, Agustín A complexity-effective local delta prefetcher 2025 Access copy available to the general public Unrestricted Data prefetching is crucial for performance in modern processors by effectively masking long-latency memory accesses. Over the past decades, numerous data prefetching mechanisms have been proposed, which have continuously reduced the access latency to the memory hierarchy. Several state-of-the-art prefetchers, namely Instruction Pointer Classifier Prefetcher (IPCP) and Berti, target the first-level data cache, and thus, they are able to completely hide the miss latency for timely prefetched cache lines. Berti exploits timely local deltas to achieve high accuracy and performance. This paper extends Berti with a larger evaluation and with extra optimizations on top of the previous conference paper. The result is a complexity-effective version of Berti that outperforms it for a large amount of workloads and simplifies its control logic. The key for those advancements is a simple mechanism for learning timely deltas without the need to track the fetch latency of each cache miss. Our experiments conducted with a wide range of workloads (CVP traces by Qualcomm, SPEC CPU2017, and GAP) show performance improvements by 4.0% over a mainstream stride prefetcher, and by a non-negligible 1.4% over the previously published version of Berti requiring similar storage. info:eu-repo/grantAgreement/ES/AEI-FEDER/RTI2018-098156-B-C53 info:eu-repo/grantAgreement/ES/AEI/PID2022-136315OB-I00 info:eu-repo/grantAgreement/ES/AEI/TED2021-130233B-C33 info:eu-repo/grantAgreement/ES/DGA/T58-23R info:eu-repo/grantAgreement/EC/H2020/101158023/EU/Energy-Efficient Highly Accurate Data Prefetching/Berti-Chip This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 101158023-Berti-Chip info:eu-repo/grantAgreement/EC/H2020/819134/EU/Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures/ECHO This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 819134-ECHO info:eu-repo/grantAgreement/ES/MICINN/PID2022-136454NB-C22 info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Panda, Biswabandan Alastruey-Benedé, Jesús Universidad de Zaragoza (orcid)0000-0003-4164-5078 Ibáñez, Pablo Universidad de Zaragoza (orcid)0000-0002-5916-7898 Viñals-Yufera, Víctor Universidad de Zaragoza (orcid)0000-0002-5976-1352 Ros, Alberto 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 74, 5 (2025), 1482-1494 IEEE trans. comput. IEEE TRANSACTIONS ON COMPUTERS 0018-9340 2749827 http://zaguan.unizar.es/record/151511/files/texto_completo.pdf Versión publicada 3311056 http://zaguan.unizar.es/record/151511/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:151511 articulos driver 2025-10-17-14:31:33 ARTICLE