000153126 001__ 153126
000153126 005__ 20251017144630.0
000153126 0247_ $$2doi$$a10.1109/ACCESS.2025.3550677
000153126 0248_ $$2sideral$$a143618
000153126 037__ $$aART-2025-143618
000153126 041__ $$aeng
000153126 100__ $$0(orcid)0000-0003-0365-6702$$aAparicio-Téllez, Raúl$$uUniversidad de Zaragoza
000153126 245__ $$aNovel Machine Learning-Resistant RO-Based PUF Optimized for IoT Device Authentication
000153126 260__ $$c2025
000153126 5060_ $$aAccess copy available to the general public$$fUnrestricted
000153126 5203_ $$aIn this work, a novel Physically Unclonable Function (PUF) based on Generalized Galois Ring Oscillators (GenGAROs) optimized for IoT device identification purposes has been proposed and analyzed. A GenGARO is composed of a certain number of logic gates with up to two inputs connected in cascade so that one input corresponds to the output of the previous gate and the other to the output of the last one. The bias of the signal of these oscillators has been used to construct a GenGARO-PUF. Firstly, the combination of logic gates which optimize the response of the GenGARO-PUF in terms of identifiability has been studied. Once the optimal configuration of GenGARO has been found, a GenGARO-PUF of 11 Look-Up Tables (LUTs) has been implemented on FPGA and its properties have been analyzed and compared to a conventional RO-PUF implemented in the exact same locations of the FPGA and using the same hard constraints. The proposal of this work shows an average Inter- Hamming Distance (HD) of 49.9 % and an Equal Error Rate EER=1.52⋅10-12 using 100-bit responses. The GenGARO-PUF has proven to outperform the conventional Ring Oscillator (RO) PUF in terms of spatial autocorrelation, uniqueness, uniformity, bit-aliasing, identifiability and resistance to modeling attacks. Furthermore, a 3-LUT GenGARO-PUF has been proposed maintaining the prediction accuracy of the 11-LUT GenGARO-PUF, and showing that a good identifiability can still be achieved using fewer resources of the FPGA.
000153126 536__ $$9info:eu-repo/grantAgreement/ES/AEI/PID2023-150244OB-I00$$9info:eu-repo/grantAgreement/ES/MICIU/PDC2023-145838-I00
000153126 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttps://creativecommons.org/licenses/by/4.0/deed.es
000153126 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion
000153126 700__ $$0(orcid)0000-0001-8648-6248$$aGarcia-Bosque, Miguel$$uUniversidad de Zaragoza
000153126 700__ $$0(orcid)0000-0001-9131-0861$$aDíez-Señorans, Guillermo
000153126 700__ $$0(orcid)0000-0003-0182-7723$$aCelma, Santiago$$uUniversidad de Zaragoza
000153126 7102_ $$15008$$2250$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Electrónica
000153126 773__ $$g13 (2025), 46147-46160$$pIEEE Access$$tIEEE Access$$x2169-3536
000153126 8564_ $$s1819538$$uhttps://zaguan.unizar.es/record/153126/files/texto_completo.pdf$$yVersión publicada
000153126 8564_ $$s2608729$$uhttps://zaguan.unizar.es/record/153126/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada
000153126 909CO $$ooai:zaguan.unizar.es:153126$$particulos$$pdriver
000153126 951__ $$a2025-10-17-14:26:15
000153126 980__ $$aARTICLE