000161798 001__ 161798 000161798 005__ 20251017144639.0 000161798 0247_ $$2doi$$a10.1109/ICCD63220.2024.00024 000161798 0248_ $$2sideral$$a144431 000161798 037__ $$aART-2025-144431 000161798 041__ $$aeng 000161798 100__ $$aToca-Díaz, Yamilka$$uUniversidad de Zaragoza 000161798 245__ $$aEnsuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage 000161798 260__ $$c2025 000161798 5060_ $$aAccess copy available to the general public$$fUnrestricted 000161798 5203_ $$aUnderscaling the supply voltage (Vdd) to ultra-low levels below the safe-operation threshold voltage (Vmin) brings significant energy savings in digital CMOS circuits but introduces reliability challenges due to increased risk of bitcell permanent faults. This work explores the impact of such faults on the accuracy of a CNN inference accelerator supplying on-chip activation memories at ultra-low Vdd. By examining fault pat-terns, activation values, and memory usage, this paper proposes two microarchitectural techniques exploiting activation outliers and activation memory underutilization. These approaches are cost-effective, do not require programmer intervention, and are application-independent. Experimental results show that the proposed approaches maintain the original CNN accuracy and achieve energy savings by 2.1 % and 8.2 % compared to the state-of-the-art technique and a conventional accelerator supplied at Vmin, respectively, with a negligible impact on the system performance (less than 0.25 %). 000161798 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58-23R$$9info:eu-repo/grantAgreement/ES/AEI/PID2022-136454NB-C22 000161798 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000161798 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion 000161798 700__ $$0(orcid)0000-0002-4031-5651$$aGran Tejero, Rubén$$uUniversidad de Zaragoza 000161798 700__ $$0(orcid)0000-0002-0824-5833$$aValero, Alejandro$$uUniversidad de Zaragoza 000161798 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000161798 773__ $$g(2025), 92-95$$tProceedings - IEEE International Conference on Computer Design$$x1063-6404 000161798 8564_ $$s226527$$uhttps://zaguan.unizar.es/record/161798/files/texto_completo.pdf$$yPostprint 000161798 8564_ $$s3108595$$uhttps://zaguan.unizar.es/record/161798/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000161798 909CO $$ooai:zaguan.unizar.es:161798$$particulos$$pdriver 000161798 951__ $$a2025-10-17-14:31:10 000161798 980__ $$aARTICLE