000163224 001__ 163224 000163224 005__ 20251020114022.0 000163224 0247_ $$2doi$$a10.1109/TVLSI.2023.3314067 000163224 0248_ $$2sideral$$a136520 000163224 037__ $$aART-2023-136520 000163224 041__ $$aeng 000163224 100__ $$aDominguez-Matas, Carlos 000163224 245__ $$aBehavioral model for high-speed SAR ADCs with on-chip references 000163224 260__ $$c2023 000163224 5060_ $$aAccess copy available to the general public$$fUnrestricted 000163224 5203_ $$aThis article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming LC package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level. 000163224 536__ $$9info:eu-repo/grantAgreement/ES/AEI/RTI2018-098513-B-I00 000163224 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000163224 590__ $$a2.8$$b2023 000163224 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b151 / 353 = 0.428$$c2023$$dQ2$$eT2 000163224 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b23 / 59 = 0.39$$c2023$$dQ2$$eT2 000163224 592__ $$a0.937$$b2023 000163224 593__ $$aElectrical and Electronic Engineering$$c2023$$dQ1 000163224 593__ $$aSoftware$$c2023$$dQ2 000163224 593__ $$aHardware and Architecture$$c2023$$dQ2 000163224 594__ $$a6.4$$b2023 000163224 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion 000163224 700__ $$aGines, Antonio 000163224 700__ $$0(orcid)0000-0003-1403-1505$$aOtin, Aranzazu$$uUniversidad de Zaragoza 000163224 700__ $$aGutiérrez, Valentín 000163224 700__ $$aLeger, Gildas 000163224 700__ $$aPeralias, Eduardo 000163224 7102_ $$15008$$2785$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Tecnología Electrónica 000163224 773__ $$g31, 12 (2023), 1918-1930$$pIEEE trans. very large scale integr. (VLSI) syst.$$tIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS$$x1063-8210 000163224 8564_ $$s6012812$$uhttps://zaguan.unizar.es/record/163224/files/texto_completo.pdf$$yPostprint 000163224 8564_ $$s3503368$$uhttps://zaguan.unizar.es/record/163224/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000163224 909CO $$ooai:zaguan.unizar.es:163224$$particulos$$pdriver 000163224 951__ $$a2025-10-20-11:13:26 000163224 980__ $$aARTICLE