doi:10.1109/TVLSI.2023.3314067engDominguez-Matas, CarlosGines, AntonioOtin, AranzazuGutiérrez, ValentínLeger, GildasPeralias, EduardoBehavioral model for high-speed SAR ADCs with on-chip referencesART-2023-136520This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming LC package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level.2023http://zaguan.unizar.es/record/16322410.1109/TVLSI.2023.3314067http://zaguan.unizar.es/record/163224oai:zaguan.unizar.es:163224info:eu-repo/grantAgreement/ES/AEI/RTI2018-098513-B-I00IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 31, 12 (2023), 1918-1930All rights reservedhttp://www.europeana.eu/rights/rr-f/info:eu-repo/semantics/openAccess