163224 20251020114022.0 doi 10.1109/TVLSI.2023.3314067 sideral 136520 ART-2023-136520 eng Dominguez-Matas, Carlos Behavioral model for high-speed SAR ADCs with on-chip references 2023 This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming LC package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level. Access copy available to the general public Unrestricted info:eu-repo/grantAgreement/ES/AEI/RTI2018-098513-B-I00 info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 2.8 2023 ENGINEERING, ELECTRICAL & ELECTRONIC 151 / 353 = 0.428 2023 Q2 T2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 23 / 59 = 0.39 2023 Q2 T2 0.937 2023 Electrical and Electronic Engineering 2023 Q1 Software 2023 Q2 Hardware and Architecture 2023 Q2 6.4 2023 info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion Gines, Antonio Otin, Aranzazu Universidad de Zaragoza (orcid)0000-0003-1403-1505 Gutiérrez, Valentín Leger, Gildas Peralias, Eduardo 5008 785 Universidad de Zaragoza Dpto. Ingeniería Electrón.Com. Área Tecnología Electrónica 31, 12 (2023), 1918-1930 IEEE trans. very large scale integr. (VLSI) syst. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1063-8210 6012812 http://zaguan.unizar.es/record/163224/files/texto_completo.pdf Postprint 3503368 http://zaguan.unizar.es/record/163224/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:163224 articulos driver 2025-10-20-11:13:26 ARTICLE