168108 20260126155509.0 doi 10.1109/PACT65351.2025.00035 sideral 147666 ART-2025-147666 eng Langarita, Rubén Squire: a general-purpose accelerator to exploit fine-grain parallelism on dependency-bound kernels 2025 Multiple HPC applications are often bottlenecked by compute-intensive kernels implementing complex dependency patterns (data-dependency bound). Traditional general-purpose accelerators struggle to effectively exploit fine-grain parallelism due to limitations in implementing convoluted data-dependency patterns (like SIMD) and overheads due to synchronization and data transfers (like GPGPUs). In contrast, custom FPGA and ASIC designs offer improved performance and energy efficiency at a high cost in hardware design and programming complexity and often lack the flexibility to process different workloads. We propose Squire, a general-purpose accelerator designed to exploit fine-grain parallelism effectively on dependency-bound kernels. Each Squire accelerator has a set of general-purpose low-power in-order cores that can rapidly communicate among themselves and directly access data from the L2 cache. Our proposal integrates one Squire accelerator per core in a typical multicore system, allowing the acceleration of dependency-bound kernels within parallel tasks with minimal software changes. As a case study, we evaluate Squire’s effectiveness by accelerating five kernels that implement complex dependency patterns. We use three of these kernels to build an end-to-end read-mapping tool that will be used to evaluate Squire. Squire obtains speedups up to 7.64× in dynamic programming kernels. Overall, Squire provides an acceleration for an end-to-end application of 3.66×. In addition, Squire reduces energy consumption by up to 56% with a minimal area overhead of 10.5% compared to a NeoverseN1 baseline. Access copy available to the general public Unrestricted info:eu-repo/grantAgreement/ES/AEI/PID2022-136454NB-C22 info:eu-repo/grantAgreement/ES/AEI/PID2023-146193OB-I00 info:eu-repo/grantAgreement/ES/DGA/T58-23R info:eu-repo/grantAgreement/ES/MICIU/PID2023-146511NB-I00 info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ info:eu-repo/semantics/conferenceObject info:eu-repo/semantics/acceptedVersion Alastruey-Benedé, Jesús Universidad de Zaragoza (orcid)0000-0003-4164-5078 Ibáñez-Marín, Pablo Universidad de Zaragoza (orcid)0000-0002-5916-7898 Marco-Sola, Santiago Moretó, Miquel Armejach, Adrià 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. (2025), 292-305 Proceedings of the Conference on Parallel Architectures and Compilation Techniques 1089-795X 453082 http://zaguan.unizar.es/record/168108/files/texto_completo.pdf Postprint 2987409 http://zaguan.unizar.es/record/168108/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:168108 articulos driver 2026-01-26-14:50:40 ARTICLE