000170186 001__ 170186 000170186 005__ 20260407115449.0 000170186 0247_ $$2doi$$a10.1109/IECON58223.2025.11221225 000170186 0248_ $$2sideral$$a148765 000170186 037__ $$aART-2025-148765 000170186 041__ $$aeng 000170186 100__ $$0(orcid)0000-0001-5709-1183$$aEnériz, Daniel 000170186 245__ $$aA High-Performance FPGA Implementation of MI-BMINet 000170186 260__ $$c2025 000170186 5203_ $$aThis paper presents the FPGA implementation of MI-BMINet, a compact and efficient Convolutional Neural Network (CNN) designed for detecting Motor-Imagery (MI) tasks in embedded Brain-Computer Interface (BCI) systems. Utilizing fpgaConvNet, the MI-BMINet model is mapped into a Synchronous Dataflow Graph (SDFG), which was then optimized for minimum latency using the SAMO tool. The SDFG was subsequently converted into a hardware description, resulting in the MI-BMINet IP, which was tested with the ZU7EV MultiProcessor Systen on Chip (MPSoC) on the ZCU104 evaluation board. A specialized driver was developed to interface with the generated IP to assess its performance. The MI-BMINet IP achieved a latency of 594 μs, surpassing the implementation on the Vega Parallel Ultra-Low Power (PULP) platform by a factor of over five, at the cost of an increased power consumption and energy per inference. To mitigate this, a power reduction study was conducted, examining the effects of adjusting the FPGA clock frequency and supply voltage on power consumption, latency, and energy per inference, finally achieving a decrease of 75% in power consumption and a reduction of 33% in energy per inference. 000170186 540__ $$9info:eu-repo/semantics/closedAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000170186 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion 000170186 700__ $$0(orcid)0000-0003-4404-776X$$aAntolín, Diego 000170186 700__ $$0(orcid)0000-0002-5380-3013$$aMedrano, Nicolás$$uUniversidad de Zaragoza 000170186 700__ $$0(orcid)0000-0003-2361-1077$$aCalvo, Belén$$uUniversidad de Zaragoza 000170186 7102_ $$15008$$2250$$aUniversidad de Zaragoza$$bDpto. Ingeniería Electrón.Com.$$cÁrea Electrónica 000170186 773__ $$g(2025), 1-6$$pAnnu. conf. IEEE Ind. Electron. Soc.$$tAnnual conference of the IEEE Industrial Electronics Society$$x2162-4704 000170186 8564_ $$s443433$$uhttps://zaguan.unizar.es/record/170186/files/texto_completo.pdf$$yPostprint 000170186 8564_ $$s797306$$uhttps://zaguan.unizar.es/record/170186/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000170186 909CO $$ooai:zaguan.unizar.es:170186$$particulos$$pdriver 000170186 951__ $$a2026-03-26-14:31:16 000170186 980__ $$aARTICLE