doi:10.1109/IECON58223.2025.11221225engEnériz, DanielAntolín, DiegoMedrano, NicolásCalvo, BelénA High-Performance FPGA Implementation of MI-BMINetART-2025-148765This paper presents the FPGA implementation of MI-BMINet, a compact and efficient Convolutional Neural Network (CNN) designed for detecting Motor-Imagery (MI) tasks in embedded Brain-Computer Interface (BCI) systems. Utilizing fpgaConvNet, the MI-BMINet model is mapped into a Synchronous Dataflow Graph (SDFG), which was then optimized for minimum latency using the SAMO tool. The SDFG was subsequently converted into a hardware description, resulting in the MI-BMINet IP, which was tested with the ZU7EV MultiProcessor Systen on Chip (MPSoC) on the ZCU104 evaluation board. A specialized driver was developed to interface with the generated IP to assess its performance. The MI-BMINet IP achieved a latency of 594 μs, surpassing the implementation on the Vega Parallel Ultra-Low Power (PULP) platform by a factor of over five, at the cost of an increased power consumption and energy per inference. To mitigate this, a power reduction study was conducted, examining the effects of adjusting the FPGA clock frequency and supply voltage on power consumption, latency, and energy per inference, finally achieving a decrease of 75% in power consumption and a reduction of 33% in energy per inference.2025http://zaguan.unizar.es/record/17018610.1109/IECON58223.2025.11221225http://zaguan.unizar.es/record/170186oai:zaguan.unizar.es:170186Annual conference of the IEEE Industrial Electronics Society (2025), 1-6All rights reservedhttp://www.europeana.eu/rights/rr-f/info:eu-repo/semantics/closedAccess