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    <subfield code="a">10.1109/IECON58223.2025.11221225</subfield>
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  <datafield tag="100" ind1=" " ind2=" ">
    <subfield code="a">Enériz, Daniel</subfield>
    <subfield code="0">(orcid)0000-0001-5709-1183</subfield>
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  <datafield tag="245" ind1=" " ind2=" ">
    <subfield code="a">A High-Performance FPGA Implementation of MI-BMINet</subfield>
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    <subfield code="c">2025</subfield>
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    <subfield code="a">This paper presents the FPGA implementation of MI-BMINet, a compact and efficient Convolutional Neural Network (CNN) designed for detecting Motor-Imagery (MI) tasks in embedded Brain-Computer Interface (BCI) systems. Utilizing fpgaConvNet, the MI-BMINet model is mapped into a Synchronous Dataflow Graph (SDFG), which was then optimized for minimum latency using the SAMO tool. The SDFG was subsequently converted into a hardware description, resulting in the MI-BMINet IP, which was tested with the ZU7EV MultiProcessor Systen on Chip (MPSoC) on the ZCU104 evaluation board. A specialized driver was developed to interface with the generated IP to assess its performance. The MI-BMINet IP achieved a latency of 594 μs, surpassing the implementation on the Vega Parallel Ultra-Low Power (PULP) platform by a factor of over five, at the cost of an increased power consumption and energy per inference. To mitigate this, a power reduction study was conducted, examining the effects of adjusting the FPGA clock frequency and supply voltage on power consumption, latency, and energy per inference, finally achieving a decrease of 75% in power consumption and a reduction of 33% in energy per inference.</subfield>
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    <subfield code="9">info:eu-repo/semantics/closedAccess</subfield>
    <subfield code="a">All rights reserved</subfield>
    <subfield code="u">http://www.europeana.eu/rights/rr-f/</subfield>
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  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="a">Antolín, Diego</subfield>
    <subfield code="0">(orcid)0000-0003-4404-776X</subfield>
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  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="a">Medrano, Nicolás</subfield>
    <subfield code="u">Universidad de Zaragoza</subfield>
    <subfield code="0">(orcid)0000-0002-5380-3013</subfield>
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  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="a">Calvo, Belén</subfield>
    <subfield code="u">Universidad de Zaragoza</subfield>
    <subfield code="0">(orcid)0000-0003-2361-1077</subfield>
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    <subfield code="1">5008</subfield>
    <subfield code="2">250</subfield>
    <subfield code="a">Universidad de Zaragoza</subfield>
    <subfield code="b">Dpto. Ingeniería Electrón.Com.</subfield>
    <subfield code="c">Área Electrónica</subfield>
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  <datafield tag="773" ind1=" " ind2=" ">
    <subfield code="g">(2025), 1-6</subfield>
    <subfield code="p">Annu. conf. IEEE Ind. Electron. Soc.</subfield>
    <subfield code="t">Annual conference of the IEEE Industrial Electronics Society</subfield>
    <subfield code="x">2162-4704</subfield>
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