000061440 001__ 61440
000061440 005__ 20190529115159.0
000061440 0247_ $$2doi$$a10.1145/2632217
000061440 0248_ $$2sideral$$a95803
000061440 037__ $$aART-2014-95803
000061440 041__ $$aeng
000061440 100__ $$0(orcid)0000-0002-7490-4067$$aSuárez Gracia, Darío$$uUniversidad de Zaragoza
000061440 245__ $$aRevisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping
000061440 260__ $$c2014
000061440 5060_ $$aAccess copy available to the general public$$fUnrestricted
000061440 5203_ $$aCache working-set adaptation is key as embedded systems move to multiprocessor and Simultaneous Multithreaded Architectures (SMT) because interthread pollution harms system performance and battery life. Light-Power NUCA (LP-NUCA) is a working-set adaptive cache that depends on temporal-locality to save energy. This work identifies the sources of energy waste in LP-NUCAs: parallel access to the tag and data arrays of the tiles and low locality phases with useless block migration. To counteract both issues, we prove that switching to serial access reduces energy without harming performance and propose a machine learning Adaptive Drop Rate (ADR) controller that minimizes the amount of replacement and migration when locality is low.
This work demonstrates that these techniques efficiently adapt the cache drop and access policies to save energy. They reduce LP-NUCA consumption 22.7% for 1SMT. With interthread cache contention in 2SMT, the savings rise to 29%. Versus a conventional organization, energy--delay improves 20.8% and 25% for 1- and 2SMT benchmarks, and, in 65% of the 2SMT mixes, gains are larger than 20%.
000061440 536__ $$9info:eu-repo/grantAgreement/ES/MINECO/DPI2011-25892$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P$$9info:eu-repo/grantAgreement/ES/MICINN/TIN2012-34557$$9info:eu-repo/grantAgreement/ES/MICINN/TIN2010-21291-C02-01$$9info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HiPEAC$$9info:eu-repo/grantAgreement/ES/DGA/T48
000061440 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000061440 590__ $$a0.503$$b2014
000061440 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b83 / 102 = 0.814$$c2014$$dQ4$$eT3
000061440 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b40 / 50 = 0.8$$c2014$$dQ4$$eT3
000061440 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/submittedVersion
000061440 700__ $$0(orcid)0000-0002-0490-8708$$aFerrerón, Alexandra$$uUniversidad de Zaragoza
000061440 700__ $$0(orcid)0000-0003-1183-349X$$aMontesano del Campo, Luis$$uUniversidad de Zaragoza
000061440 700__ $$aMonreal Arnal, Teresa
000061440 700__ $$0(orcid)0000-0002-5976-1352$$aViñals Yúfera, Víctor$$uUniversidad de Zaragoza
000061440 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000061440 7102_ $$15007$$2570$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Lenguajes y Sistemas Inf.
000061440 773__ $$g11, 2 (2014), 19 [26 pp.]$$pACM Transactions on Architecture and Code Optimization$$tACM Transactions on Architecture and Code Optimization$$x1544-3566
000061440 8564_ $$s962728$$uhttps://zaguan.unizar.es/record/61440/files/texto_completo.pdf$$yPreprint
000061440 8564_ $$s57694$$uhttps://zaguan.unizar.es/record/61440/files/texto_completo.jpg?subformat=icon$$xicon$$yPreprint
000061440 909CO $$ooai:zaguan.unizar.es:61440$$particulos$$pdriver
000061440 951__ $$a2019-05-29-11:36:39
000061440 980__ $$aARTICLE