<?xml version="1.0" encoding="UTF-8"?>
<xml>
<records>
<record>
  <contributors>
    <authors>
      <author>Clemente, Juan Antonio</author>
      <author>Gran Tejero, Rubén</author>
      <author>Chocano, Abel</author>
      <author>del Prado, Carlos</author>
      <author>Resano, Javier</author>
    </authors>
  </contributors>
  <titles>
    <title>Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems</title>
    <secondary-title>IEEE trans. very large scale integr. (VLSI) syst.</secondary-title>
  </titles>
  <doi>10.1109/TVLSI.2015.2417595</doi>
  <pages/>
  <volume/>
  <number/>
  <dates>
    <year>2015</year>
    <pub-dates>
      <date>2015</date>
    </pub-dates>
  </dates>
  <abstract/>
</record>

</records>
</xml>