69448 20210121114533.0 doi 10.1109/TVLSI.2015.2417595 sideral 91762 ART-2015-91762 eng Clemente, Juan Antonio Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems 2015 Access copy available to the general public Unrestricted The efficiency of the reconfiguration process in modern field-programmable gate arrays (FPGAs) can improve drastically if an on-chip configuration memory is included in the system, because it can reduce both the reconfiguration latency and its energy consumption. However, the FPGA on-chip memory resources are very limited. Thus, it is very important to manage them effectively in order to improve the reconfiguration process as much as possible, even when the size of the on-chip configuration memory is small. This paper presents a hardware implementation of an on-chip configuration memory controller that efficiently manages run-time reconfigurations. In order to optimize the use of the on-chip memory, this controller includes support to deal with configurations that have been divided into blocks of customizable size. When a reconfiguration must be carried out, our controller provides the blocks stored on-chip and looks for the remaining blocks by accessing to the off-chip configuration memory. Moreover, it dynamically decides which blocks must be stored on-chip. To this end, the designed controller implements a simple but efficient technique that allows maximizing the benefits of the on-chip memories. Experimental results will demonstrate that its implementation cost is very affordable and that it introduces negligible run-time management overheads. info:eu-repo/grantAgreement/ES/MINECO/TIN2013-40968-P info:eu-repo/grantAgreement/ES/MINECO/AYA2009-13300 info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P info:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HiPEAC info:eu-repo/grantAgreement/ES/DGA/T48 info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 1.245 2015 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 19 / 51 = 0.373 2015 Q2 T2 ENGINEERING, ELECTRICAL & ELECTRONIC 132 / 257 = 0.514 2015 Q3 T2 0.592 2015 Electrical and Electronic Engineering 2015 Q2 Software 2015 Q2 Hardware and Architecture 2015 Q2 info:eu-repo/semantics/article info:eu-repo/semantics/submittedVersion (orcid)0000-0002-4031-5651 Gran Tejero, Rubén Universidad de Zaragoza Chocano, Abel del Prado, Carlos (orcid)0000-0002-7532-2720 Resano, Javier Universidad de Zaragoza 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 24, 2 (2015), 530 - 543 IEEE trans. very large scale integr. (VLSI) syst. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1063-8210 494316 http://zaguan.unizar.es/record/69448/files/texto_completo.pdf Preprint 131048 http://zaguan.unizar.es/record/69448/files/texto_completo.jpg?subformat=icon icon Preprint oai:zaguan.unizar.es:69448 articulos driver 2021-01-21-11:11:54 ARTICLE