000069450 001__ 69450
000069450 005__ 20180320152106.0
000069450 0247_ $$2doi$$a10.1016/j.micpro.2015.01.001
000069450 0248_ $$2sideral$$a89763
000069450 037__ $$aART-2015-89763
000069450 041__ $$aeng
000069450 100__ $$aOlivito, J.
000069450 245__ $$aPerformance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors
000069450 260__ $$c2015
000069450 5060_ $$aAccess copy available to the general public$$fUnrestricted
000069450 5203_ $$aBoard-game applications are frequently found in mobile devices where the computing performance and the energy budget are constrained. Since the Artificial Intelligence techniques applied in these games are computationally intensive, the applications developed for mobile systems are frequently simplistic, far from the level of equivalent applications developed for desktop computers.
Currently board games are software applications executed on General Purpose Processors. However, they exhibit a medium degree of parallelism and a custom hardware accelerator implemented on an FPGA can take advantage of that.
We have selected the well-known Reversi game as a case study because it is a very popular board game with simple rules but huge computational demands. We developed and optimized software and hardware designs for this game that apply the same classical Artificial Intelligence techniques. The applications have been executed on different representative platforms and the results demonstrate that the FPGAs implementations provide better performance, lower power consumption and, therefore, impressive energy savings. These results demonstrate that FPGAs can efficiently deal with this kind of problems.
000069450 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T48$$9info:eu-repo/grantAgreement/ES/MICINN/TIN2010-21291-C02-01$$9info:eu-repo/grantAgreement/ES/MINECO/CSD2007-00050
000069450 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000069450 590__ $$a0.471$$b2015
000069450 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b44 / 51 = 0.863$$c2015$$dQ4$$eT3
000069450 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b215 / 255 = 0.843$$c2015$$dQ4$$eT3
000069450 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b97 / 105 = 0.924$$c2015$$dQ4$$eT3
000069450 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/submittedVersion
000069450 700__ $$0(orcid)0000-0002-4031-5651$$aGran, R.$$uUniversidad de Zaragoza
000069450 700__ $$0(orcid)0000-0002-7532-2720$$aResano, J.$$uUniversidad de Zaragoza
000069450 700__ $$aGonzález, C.
000069450 700__ $$0(orcid)0000-0001-8093-8346$$aTorres, E.$$uUniversidad de Zaragoza
000069450 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDepartamento de Informática e Ingeniería de Sistemas$$cArquitectura y Tecnología de Computadores
000069450 773__ $$g39, 2 (2015), 64-73$$pMicroprocess. microsyst.$$tMICROPROCESSORS AND MICROSYSTEMS$$x0141-9331
000069450 8564_ $$s696767$$uhttps://zaguan.unizar.es/record/69450/files/texto_completo.pdf$$yPreprint
000069450 8564_ $$s91392$$uhttps://zaguan.unizar.es/record/69450/files/texto_completo.jpg?subformat=icon$$xicon$$yPreprint
000069450 909CO $$ooai:zaguan.unizar.es:69450$$particulos$$pdriver
000069450 951__ $$a2018-03-20-15:11:48
000069450 980__ $$aARTICLE