doi:10.1049/iet-cdt.2016.0095engOlivito, JavierSerrano, FelipeClemente, Juan AntonioMecha, HortensiaResano, JavierAnalysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGAART-2018-104913In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.2018http://zaguan.unizar.es/record/6946510.1049/iet-cdt.2016.0095http://zaguan.unizar.es/record/69465oai:zaguan.unizar.es:69465info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-Pinfo:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDCIET Computers and Digital Techniques 12, 4 (2018), [33 pp]All rights reservedhttp://www.europeana.eu/rights/rr-f/info:eu-repo/semantics/openAccess