69465 20210226081039.0 doi 10.1049/iet-cdt.2016.0095 sideral 104913 ART-2018-104913 eng (orcid)0000-0002-7752-8714 Olivito, Javier Universidad de Zaragoza Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA 2018 Access copy available to the general public Unrestricted In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead. info:eu-repo/grantAgreement/ES/MINECO/TIN2013-46957-C2-1-P info:eu-repo/grantAgreement/ES/MINECO/TIN2014-52608-REDC info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 0.857 2018 COMPUTER SCIENCE, THEORY & METHODS 75 / 104 = 0.721 2018 Q3 T3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 46 / 52 = 0.885 2018 Q4 T3 0.19 2018 Electrical and Electronic Engineering 2018 Q3 Software 2018 Q3 Hardware and Architecture 2018 Q3 info:eu-repo/semantics/article info:eu-repo/semantics/submittedVersion Serrano, Felipe Clemente, Juan Antonio Mecha, Hortensia (orcid)0000-0002-7532-2720 Resano, Javier Universidad de Zaragoza 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 12, 4 (2018), [33 pp] IET Computers and Digital Techniques IET Computers and Digital Techniques 1751-8601 1018421 http://zaguan.unizar.es/record/69465/files/texto_completo.pdf Preprint 98992 http://zaguan.unizar.es/record/69465/files/texto_completo.jpg?subformat=icon icon Preprint oai:zaguan.unizar.es:69465 articulos driver 2021-02-26-07:56:11 ARTICLE