<?xml version="1.0" encoding="UTF-8"?>
<references>
<reference>
  <a1>Olivito, Javier</a1>
  <a2>Serrano, Felipe</a2>
  <a2>Clemente, Juan Antonio</a2>
  <a2>Mecha, Hortensia</a2>
  <a2>Resano, Javier</a2>
  <t1>Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA</t1>
  <t2>IET Computers and Digital Techniques</t2>
  <sn/>
  <op/>
  <vo/>
  <ab/>
  <la>eng</la>
  <k1/>
  <pb/>
  <pp/>
  <yr>2018</yr>
  <ed/>
  <ul>http://zaguan.unizar.es/record/69465/files/texto_completo.pdf;
	http://zaguan.unizar.es/record/69465/files/texto_completo.jpg?subformat=icon;
	</ul>
  <no>Imported from Invenio.</no>
</reference>

</references>