000070277 001__ 70277 000070277 005__ 20220120225831.0 000070277 0247_ $$2doi$$a10.1007/s11227-018-2367-9 000070277 0248_ $$2sideral$$a105895 000070277 037__ $$aART-2018-105895 000070277 041__ $$aeng 000070277 100__ $$aNunez-Yanez, J. 000070277 245__ $$aSimultaneous multiprocessing in a software-defined heterogeneous FPGA 000070277 260__ $$c2018 000070277 5060_ $$aAccess copy available to the general public$$fUnrestricted 000070277 5203_ $$aHeterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the utilization of all the available CPU cores in parallel with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution. 000070277 540__ $$9info:eu-repo/semantics/openAccess$$aby$$uhttp://creativecommons.org/licenses/by/3.0/es/ 000070277 590__ $$a2.157$$b2018 000070277 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b22 / 52 = 0.423$$c2018$$dQ2$$eT2 000070277 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b132 / 265 = 0.498$$c2018$$dQ2$$eT2 000070277 591__ $$aCOMPUTER SCIENCE, THEORY & METHODS$$b35 / 104 = 0.337$$c2018$$dQ2$$eT2 000070277 592__ $$a0.385$$b2018 000070277 593__ $$aHardware and Architecture$$c2018$$dQ2 000070277 593__ $$aTheoretical Computer Science$$c2018$$dQ2 000070277 593__ $$aSoftware$$c2018$$dQ2 000070277 593__ $$aInformation Systems$$c2018$$dQ2 000070277 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/publishedVersion 000070277 700__ $$aAmiri, S. 000070277 700__ $$aHosseinabady, M. 000070277 700__ $$aRodríguez, A. 000070277 700__ $$aAsenjo, R. 000070277 700__ $$aNavarro, A. 000070277 700__ $$0(orcid)0000-0002-7490-4067$$aSuarez, D.$$uUniversidad de Zaragoza 000070277 700__ $$0(orcid)0000-0002-4031-5651$$aGran, R.$$uUniversidad de Zaragoza 000070277 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000070277 773__ $$g75 (2018), 4078 - 4095$$pJ. supercomput.$$tJournal of Supercomputing$$x0920-8542 000070277 8564_ $$s1288697$$uhttps://zaguan.unizar.es/record/70277/files/texto_completo.pdf$$yVersión publicada 000070277 8564_ $$s6500$$uhttps://zaguan.unizar.es/record/70277/files/texto_completo.jpg?subformat=icon$$xicon$$yVersión publicada 000070277 909CO $$ooai:zaguan.unizar.es:70277$$particulos$$pdriver 000070277 951__ $$a2022-01-20-22:54:49 000070277 980__ $$aARTICLE