70277 20220120225831.0 doi 10.1007/s11227-018-2367-9 sideral 105895 ART-2018-105895 eng Nunez-Yanez, J. Simultaneous multiprocessing in a software-defined heterogeneous FPGA 2018 Access copy available to the general public Unrestricted Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the utilization of all the available CPU cores in parallel with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution. info:eu-repo/semantics/openAccess by http://creativecommons.org/licenses/by/3.0/es/ 2.157 2018 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 22 / 52 = 0.423 2018 Q2 T2 ENGINEERING, ELECTRICAL & ELECTRONIC 132 / 265 = 0.498 2018 Q2 T2 COMPUTER SCIENCE, THEORY & METHODS 35 / 104 = 0.337 2018 Q2 T2 0.385 2018 Hardware and Architecture 2018 Q2 Theoretical Computer Science 2018 Q2 Software 2018 Q2 Information Systems 2018 Q2 info:eu-repo/semantics/article info:eu-repo/semantics/publishedVersion Amiri, S. Hosseinabady, M. Rodríguez, A. Asenjo, R. Navarro, A. Suarez, D. Universidad de Zaragoza (orcid)0000-0002-7490-4067 Gran, R. Universidad de Zaragoza (orcid)0000-0002-4031-5651 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 75 (2018), 4078 - 4095 J. supercomput. Journal of Supercomputing 0920-8542 1288697 http://zaguan.unizar.es/record/70277/files/texto_completo.pdf Versión publicada 6500 http://zaguan.unizar.es/record/70277/files/texto_completo.jpg?subformat=icon icon Versión publicada oai:zaguan.unizar.es:70277 articulos driver 2022-01-20-22:54:49 ARTICLE