000075456 001__ 75456 000075456 005__ 20200117221609.0 000075456 0247_ $$2doi$$a10.1109/TVLSI.2018.2831665 000075456 0248_ $$2sideral$$a107903 000075456 037__ $$aART-2018-107903 000075456 041__ $$aeng 000075456 100__ $$aTrapani Possignolo, Rafael 000075456 245__ $$aGPU NTC Process Variation Compensation with Voltage Stacking 000075456 260__ $$c2018 000075456 5060_ $$aAccess copy available to the general public$$fUnrestricted 000075456 5203_ $$aNear-threshold computing (NTC) has the potential to significantly improve efficiency in high throughput architectures, such as general-purpose computing on graphic processing unit (GPGPU). Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without PV management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-PV case, delivering on average (across chips) ˜80 % of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ˜50 % of the nominal performance. We also show that our approach can be applied on top of multifrequency domain designs, improving the overall performance. 000075456 536__ $$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R$$9This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 687698-HiPEAC$$9info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC$$9info:eu-repo/grantAgreement/ES/DGA/T48 000075456 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/ 000075456 590__ $$a1.946$$b2018 000075456 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b26 / 52 = 0.5$$c2018$$dQ2$$eT2 000075456 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b146 / 265 = 0.551$$c2018$$dQ3$$eT2 000075456 592__ $$a0.405$$b2018 000075456 593__ $$aElectrical and Electronic Engineering$$c2018$$dQ2 000075456 593__ $$aSoftware$$c2018$$dQ2 000075456 593__ $$aHardware and Architecture$$c2018$$dQ2 000075456 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion 000075456 700__ $$aEbrahimi, Elnaz 000075456 700__ $$aArdestani, Ehsan 000075456 700__ $$aSankaranarayanan, Alamelu 000075456 700__ $$0(orcid)0000-0001-5940-9837$$aBriz Velasco, Jose Luis$$uUniversidad de Zaragoza 000075456 700__ $$aRenau, Jose 000075456 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput. 000075456 773__ $$g26, 9 (2018), 1713-1726$$pIEEE trans. very large scale integr. (VLSI) syst.$$tIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS$$x1063-8210 000075456 8564_ $$s5009791$$uhttps://zaguan.unizar.es/record/75456/files/texto_completo.pdf$$yPostprint 000075456 8564_ $$s8427$$uhttps://zaguan.unizar.es/record/75456/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint 000075456 909CO $$ooai:zaguan.unizar.es:75456$$particulos$$pdriver 000075456 951__ $$a2020-01-17-21:47:46 000075456 980__ $$aARTICLE