75456 20200117221609.0 doi 10.1109/TVLSI.2018.2831665 sideral 107903 ART-2018-107903 eng Trapani Possignolo, Rafael GPU NTC Process Variation Compensation with Voltage Stacking 2018 Access copy available to the general public Unrestricted Near-threshold computing (NTC) has the potential to significantly improve efficiency in high throughput architectures, such as general-purpose computing on graphic processing unit (GPGPU). Nevertheless, NTC is more sensitive to process variation (PV) as it complicates power delivery. We propose GPU stacking, a novel method based on voltage stacking, to manage the effects of PV and improve the power delivery simultaneously. To evaluate our methodology, we first explore the design space of GPGPUs in the NTC to find a suitable baseline configuration and then apply GPU stacking to mitigate the effects of PV. When comparing with an equivalent NTC GPGPU without PV management, we achieve 37% more performance on average. When considering high production volume, our approach shifts all the chips closer to the nominal non-PV case, delivering on average (across chips) ˜80 % of the performance of nominal NTC GPGPU, whereas when not using our technique, chips would have ˜50 % of the nominal performance. We also show that our approach can be applied on top of multifrequency domain designs, improving the overall performance. info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 687698-HiPEAC info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC info:eu-repo/grantAgreement/ES/DGA/T48 info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 1.946 2018 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 26 / 52 = 0.5 2018 Q2 T2 ENGINEERING, ELECTRICAL & ELECTRONIC 146 / 265 = 0.551 2018 Q3 T2 0.405 2018 Electrical and Electronic Engineering 2018 Q2 Software 2018 Q2 Hardware and Architecture 2018 Q2 info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion Ebrahimi, Elnaz Ardestani, Ehsan Sankaranarayanan, Alamelu (orcid)0000-0001-5940-9837 Briz Velasco, Jose Luis Universidad de Zaragoza Renau, Jose 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 26, 9 (2018), 1713-1726 IEEE trans. very large scale integr. (VLSI) syst. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1063-8210 5009791 http://zaguan.unizar.es/record/75456/files/texto_completo.pdf Postprint 8427 http://zaguan.unizar.es/record/75456/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:75456 articulos driver 2020-01-17-21:47:46 ARTICLE