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<dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:invenio="http://invenio-software.org/elements/1.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><dc:identifier>doi:10.3390/electronics7120423</dc:identifier><dc:language>eng</dc:language><dc:creator>Martinez-Nieto, J.A.</dc:creator><dc:creator>Sanz-Pascual, M.T.</dc:creator><dc:creator>Medrano-Marques, N.</dc:creator><dc:creator>Calvo-Lopez, B.</dc:creator><dc:creator>Sarmiento-Reyes, A.</dc:creator><dc:title>High-Linearity Self-Biased CMOS Current Buffer</dc:title><dc:identifier>ART-2018-110463</dc:identifier><dc:description>A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications.</dc:description><dc:date>2018</dc:date><dc:source>http://zaguan.unizar.es/record/77196</dc:source><dc:doi>10.3390/electronics7120423</dc:doi><dc:identifier>http://zaguan.unizar.es/record/77196</dc:identifier><dc:identifier>oai:zaguan.unizar.es:77196</dc:identifier><dc:relation>info:eu-repo/grantAgreement/ES/MINECO-FEDER/TEC2015-65750-R</dc:relation><dc:identifier.citation>ELECTRONICS 7, 12 (2018), 423 [18 pp]</dc:identifier.citation><dc:rights>by</dc:rights><dc:rights>http://creativecommons.org/licenses/by/3.0/es/</dc:rights><dc:rights>info:eu-repo/semantics/openAccess</dc:rights></dc:dc>

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