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000079570 0247_ $$2doi$$a10.1109/TC.2018.2849376
000079570 0248_ $$2sideral$$a107642
000079570 037__ $$aART-2019-107642
000079570 041__ $$aeng
000079570 100__ $$0(orcid)0000-0002-0824-5833$$aValero Bresó, Alejandro$$uUniversidad de Zaragoza
000079570 245__ $$aAn aging-aware GPU register file design based on data redundancy
000079570 260__ $$c2019
000079570 5060_ $$aAccess copy available to the general public$$fUnrestricted
000079570 5203_ $$aNowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage Vth over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall Vth degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100% ‘0’ and ‘1’ duty cycle distributions). On average, the proposal reduces these distributions by 58% and 68%, respectively, which translates into Vth degradation savings by 54% and 62%, respectively.
000079570 536__ $$9info:eu-repo/grantAgreement/ES/DGA/T58-17R$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2015-66972-C5-1-R$$9info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R
000079570 540__ $$9info:eu-repo/semantics/openAccess$$aAll rights reserved$$uhttp://www.europeana.eu/rights/rr-f/
000079570 590__ $$a2.711$$b2019
000079570 591__ $$aENGINEERING, ELECTRICAL & ELECTRONIC$$b111 / 266 = 0.417$$c2019$$dQ2$$eT2
000079570 591__ $$aCOMPUTER SCIENCE, HARDWARE & ARCHITECTURE$$b19 / 53 = 0.358$$c2019$$dQ2$$eT2
000079570 592__ $$a0.943$$b2019
000079570 593__ $$aComputational Theory and Mathematics$$c2019$$dQ1
000079570 593__ $$aTheoretical Computer Science$$c2019$$dQ1
000079570 593__ $$aSoftware$$c2019$$dQ1
000079570 593__ $$aHardware and Architecture$$c2019$$dQ1
000079570 655_4 $$ainfo:eu-repo/semantics/article$$vinfo:eu-repo/semantics/acceptedVersion
000079570 700__ $$aCandel Margaix, Francisco
000079570 700__ $$0(orcid)0000-0002-7490-4067$$aSuárez Gracia, Darío$$uUniversidad de Zaragoza
000079570 700__ $$aPetit Martí, Salvador Vicente
000079570 700__ $$aSahuquillo Borrás, Julio
000079570 7102_ $$15007$$2035$$aUniversidad de Zaragoza$$bDpto. Informát.Ingenie.Sistms.$$cÁrea Arquit.Tecnología Comput.
000079570 773__ $$g68, 1 (2019), 4-20$$pIEEE trans. comput.$$tIEEE TRANSACTIONS ON COMPUTERS$$x0018-9340
000079570 8564_ $$s1840160$$uhttps://zaguan.unizar.es/record/79570/files/texto_completo.pdf$$yPostprint
000079570 8564_ $$s132032$$uhttps://zaguan.unizar.es/record/79570/files/texto_completo.jpg?subformat=icon$$xicon$$yPostprint
000079570 909CO $$ooai:zaguan.unizar.es:79570$$particulos$$pdriver
000079570 951__ $$a2022-01-20-22:55:21
000079570 980__ $$aARTICLE