79570 20220120225832.0 doi 10.1109/TC.2018.2849376 sideral 107642 ART-2019-107642 eng Valero Bresó, Alejandro Universidad de Zaragoza (orcid)0000-0002-0824-5833 An aging-aware GPU register file design based on data redundancy 2019 Access copy available to the general public Unrestricted Nowadays, GPUs sit at the forefront of high-performance computing thanks to their massive computational capabilities. Internally, thousands of functional units, architected to be fed by large register files, fuel such a performance. At deep nanometer technologies, the SRAM memory cells that implement GPU register files are very sensitive to the Negative Bias Temperature Instability (NBTI) effect. NBTI ages cell transistors by degrading their threshold voltage Vth over the lifetime of the GPU. This degradation, which manifests when a cell keeps the same logic value for a relatively long period of time, compromises the cell read stability and increases the transistor switching delay, which can lead to wrong read values and eventually exceed the processor cycle time, respectively, so resulting in faulty operation. This work proposes architectural mechanisms leveraging the redundancy of the data stored in GPU register files to attack NBTI aging. The proposed mechanisms are based on data compression, power gating, and register address rotation techniques. All these mechanisms working together balance the distribution of logic values stored in the cells along the execution time, reducing both the overall Vth degradation and the increase in the transistor switching delays. Experimental results show that a conventional GPU register file suffers the worst case for NBTI, since a significant fraction of the cells maintain the same logic value during the entire application execution (i.e., a 100% ‘0’ and ‘1’ duty cycle distributions). On average, the proposal reduces these distributions by 58% and 68%, respectively, which translates into Vth degradation savings by 54% and 62%, respectively. info:eu-repo/grantAgreement/ES/DGA/T58-17R info:eu-repo/grantAgreement/ES/MINECO/TIN2015-66972-C5-1-R info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 2.711 2019 ENGINEERING, ELECTRICAL & ELECTRONIC 111 / 266 = 0.417 2019 Q2 T2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 19 / 53 = 0.358 2019 Q2 T2 0.943 2019 Computational Theory and Mathematics 2019 Q1 Theoretical Computer Science 2019 Q1 Software 2019 Q1 Hardware and Architecture 2019 Q1 info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion Candel Margaix, Francisco Suárez Gracia, Darío Universidad de Zaragoza (orcid)0000-0002-7490-4067 Petit Martí, Salvador Vicente Sahuquillo Borrás, Julio 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 68, 1 (2019), 4-20 IEEE trans. comput. IEEE TRANSACTIONS ON COMPUTERS 0018-9340 1840160 http://zaguan.unizar.es/record/79570/files/texto_completo.pdf Postprint 132032 http://zaguan.unizar.es/record/79570/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:79570 articulos driver 2022-01-20-22:55:21 ARTICLE