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<dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:invenio="http://invenio-software.org/elements/1.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><dc:identifier>doi:10.1016/j.ifacol.2018.06.307</dc:identifier><dc:language>eng</dc:language><dc:creator>Rubio-Anguiano, L.</dc:creator><dc:creator>Desirena-López, G.</dc:creator><dc:creator>Ramírez-Treviño, A.</dc:creator><dc:creator>Briz, J.L.</dc:creator><dc:title>Energy-Efficient Thermal-Aware Scheduling for RT Tasks Using TCPN</dc:title><dc:identifier>ART-2018-107586</dc:identifier><dc:description>This work leverages TCPNs to design an energy-efficient, thermal-aware real-time scheduler for a multiprocessor system that normally runs in a low state energy at maximum system utilization but its capable of increasing the clock frequency to serve aperiodic tasks, optimizing energy, and honoring temporal and thermal constraints. An off-line stage computes the minimum frequency required to run the periodic tasks at maximum CPU utilization, the proportion of each task''s job to be run on each CPU, the maximum clock frequency that keeps temperature under a limit, and the available cycles (slack) with respect to the system with minimum frequency. Then, a Zero-Laxity online scheduler dispatches the periodic tasks according to the offline calculation. Upon the arrival of aperiodic tasks, it increases clock frequency in such a way that all periodic and aperiodic tasks are properly executed. Thermal and temporal requirements are always guaranteed, and energy consumption is minimized.</dc:description><dc:date>2018</dc:date><dc:source>http://zaguan.unizar.es/record/79731</dc:source><dc:doi>10.1016/j.ifacol.2018.06.307</dc:doi><dc:identifier>http://zaguan.unizar.es/record/79731</dc:identifier><dc:identifier>oai:zaguan.unizar.es:79731</dc:identifier><dc:relation>info:eu-repo/grantAgreement/ES/DGA/T48</dc:relation><dc:relation>info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC</dc:relation><dc:relation>This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No H2020 687698-HiPEAC</dc:relation><dc:relation>info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R</dc:relation><dc:identifier.citation>IFAC PAPERSONLINE 51, 7 (2018), 236-242</dc:identifier.citation><dc:rights>All rights reserved</dc:rights><dc:rights>http://www.europeana.eu/rights/rr-f/</dc:rights><dc:rights>info:eu-repo/semantics/openAccess</dc:rights></dc:dc>

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