84684 20210303162448.0 doi 10.1016/j.jpdc.2018.10.010 sideral 109702 ART-2019-109702 eng (orcid)0000-0002-0490-8708 Ferrerón, A. A fault-tolerant last level cache for CMPs operating at ultra-low voltage 2019 Access copy available to the general public Unrestricted Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that allows low-voltage operation by deactivating faulty cache entries, at the expense of reducing the effective cache capacity. In the case of the last-level cache, this capacity reduction leads to an increase in off-chip memory accesses, diminishing the overall energy benefit of reducing the voltage supply. In this work, we exploit the reuse locality and the intrinsic redundancy of multi-level inclusive hierarchies to enhance the performance of block disabling with negligible cost. The proposed fault-aware last-level cache management policy maps critical blocks, those not present in private caches and with a higher probability of being reused, to active cache entries. Our evaluation shows that this fault-aware management results in up to 37.3% and 54.2% fewer misses per kilo instruction (MPKI) than block disabling for multiprogrammed and parallel workloads, respectively. This translates to performance enhancements of up to 13% and 34.6% for multiprogrammed and parallel workloads, respectively. info:eu-repo/grantAgreement/ES/DGA/T58-17R info:eu-repo/grantAgreement/ES/MINECO/TIN2015-65316-P info:eu-repo/grantAgreement/ES/MINECO/TIN2016-76635-C2-1-R info:eu-repo/semantics/openAccess All rights reserved http://www.europeana.eu/rights/rr-f/ 2.296 2019 0.525 2019 COMPUTER SCIENCE, THEORY & METHODS 35 / 108 = 0.324 2019 Q2 T1 Artificial Intelligence 2019 Q2 Computer Networks and Communications 2019 Q2 Hardware and Architecture 2019 Q2 Software 2019 Q2 Theoretical Computer Science 2019 Q3 info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion (orcid)0000-0003-4164-5078 Alastruey-Benedé, J. Universidad de Zaragoza (orcid)0000-0002-7490-4067 Suárez Gracia, D. Universidad de Zaragoza Monreal Arnal, T. (orcid)0000-0002-5916-7898 Ibáñez Marín, P. Universidad de Zaragoza (orcid)0000-0002-5976-1352 Viñals Yúfera, V. Universidad de Zaragoza 5007 035 Universidad de Zaragoza Dpto. Informát.Ingenie.Sistms. Área Arquit.Tecnología Comput. 125 (2019), 31-44 J. parallel distrib. comput. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 0743-7315 1745581 http://zaguan.unizar.es/record/84684/files/texto_completo.pdf Postprint 162562 http://zaguan.unizar.es/record/84684/files/texto_completo.jpg?subformat=icon icon Postprint oai:zaguan.unizar.es:84684 articulos driver 2021-03-03-16:11:01 ARTICLE